RMLV0808BGSB - 4S2
R10DS0232EJ0200 Rev.2.00 Page 8 of
11
2015.06.26
Write Cycle (1) (WE# CLOCK, OE#=”H” while writing)
Note 17. t
WP
is the interval between write start and write end.
A write starts when all of (CS1#), (WE#) and (CS2) become active.
A write is performed during the overlap of a low CS1#, a low WE# and a high CS2.
A write ends when any of (CS1#), (WE#) or (CS2) becomes inactive.
18. t
OHZ
and t
WHZ
are defined as the time when the DQ pins enter a high-impedance state and are not referred to
the DQ levels.
19. This parameter is sampled and not 100% tested
20. During this period, DQ pins are in the output state so input signals must not be applied to the DQ pins.
CS1#
A
0~19
t
CW
t
WHZ
OE#
WE#
DQ
0~7
t
DH
t
WC
CS2
t
CW
Valid address
t
WR
t
AW
t
AS
t
WP
t
DW
*17
*18,19
*18,19
t
OHZ
Valid Data
*20
