MAX9122EUE+T Datasheet MAX9122EUE+T, MAX9122EUE+, MAX9121EUE+ | P4-P6

MAX9121/MAX9122

Quad LVDS Line Receivers with

Integrated Termination and Flow-Through Pinout

4 _______________________________________________________________________________________

Typical Operating Characteristics

= +3.3V, V

= +1.2V, |V

| = 0.2V, C

= 15pF, T

= +25°C, unless otherwise noted.) (Figures 2 and 3)

0.01 0.1 1000100

SUPPLY CURRENT

vs. FREQUENCY

MAX9121/22 toc01

FREQUENCY (MHz)

SUPPLY CURRENT (mA)

110

ALL

CHANNELS

SWITCHING

ONE

SWITCHING

7.00

7.50

8.00

8.50

9.00

9.50

10.00

10.50

11.00

-40 -15 10 35 60 85

SUPPLY CURRENT vs.

TEMPERATURE

MAX9121/22 toc02

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

3.0 3.3 3.6

DIFFERENTIAL THRESHOLD VOLTAGE

vs. SUPPLY VOLTAGE

MAX9121/22 toc03

SUPPLY VOLTAGE (V)

DIFFERENTIAL THRESHOLD VOLTAGE (mV)

Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground

except V

, V

, and V

Note 2: Short only one output at a time. Do not exceed the absolute maximum junction temperature specification.

Note 3: AC parameters are guaranteed by design and characterization.

Note 4: C

includes scope probe and test jig capacitance.

Note 5: t

SKD1

is the magnitude difference of differential propagation delays in a channel. t

SKD1

= |t

PHLD

- t

PLHD

Note 6: t

SKD2

is the magnitude difference of the t

PLHD

or t

PHLD

of one channel and the t

PLHD

or t

PHLD

of any other channel on the same part.

Note 7: t

SKD3

is the magnitude difference of any differential propagation delays between parts operating over rated conditions at

the same V

and within 5°C of each other.

Note 8: t

SKD4

is the magnitude difference of any differential propagation delays between parts operating over rated conditions.

Note 9: f

MAX

generator output conditions: rise-time = fall-time = 1ns (0% to 100%), 50% duty cycle, V

= +1.3V, V

= +1.1V,

MAX9121/MAX9122 output criteria: 60% to 40% duty cycle, V

= 0.4V (max), V

= 2.7V (min), load = 15pF.

3.0 3.3 3.6

OUTPUT SHORT-CIRCUIT CURRENT

vs. SUPPLY VOLTAGE

MAX9121/22 toc04

SUPPLY VOLTAGE (V)

OUTPUT SHORT-CIRCUIT CURRENT (mA)

-70

-75

-80

-65

-90

-95

-85

1.30

1.25

1.20

1.15

1.10

3.0 3.3 3.6

OUTPUT HIGH-IMPEDANCE CURRENT

vs. SUPPLY VOLTAGE

MAX9121/22 toc05

SUPPLY VOLTAGE (V)

OUTPUT HIGH-IMPEDANCE CURRENT (nA)

2.7

2.9

3.3

3.1

3.5

3.7

3.0 3.3 3.6

OUTPUT HIGH VOLTAGE vs.

SUPPLY VOLTAGE

MAX9121/22 toc06

SUPPLY VOLTAGE (V)

OUTPUT HIGH VOLTAGE (V)

AC ELECTRICAL CHARACTERISTICS (continued)

= +3.0V to +3.6V, C

= 15pF, differential input voltage |V

| = 0.2V to 1.0V, common-mode voltage V

= |V

/2| to 2.4V -

/2|, input rise and fall time = 1ns (20% to 80%), input frequency = 100MHz, T

= -40°C to +85°C. Typical values are at V

+3.3V, V

= 1.2V, |V

| = 0.2V, T

= +25°C, unless otherwise noted.) (Notes 3, 4)

MAX9121/MAX9122

Quad LVDS Line Receivers with

Integrated Termination and Flow-Through Pinout

_______________________________________________________________________________________ 5

Typical Operating Characteristics (continued)

= +3.3V, V

= +1.2V, |V

| = 0.2V, C

= 15pF, T

= +25°C, unless otherwise noted.) (Figures 2 and 3)

600

575

550

525

500

3.0 3.3 3.6

TRANSITION TIME vs.

SUPPLY VOLTAGE

MAX9121/22 toc13

SUPPLY VOLTAGE (V)

TRANSITION TIME (ps)

TLH

THL

450

475

500

525

550

575

600

625

650

-40 -15 10 35 60 85

TRANSITION TIME vs.

TEMPERATURE

MAX9121/22 toc14

TEMPERATURE (°C)

TRANSITION TIME (ps)

TLH

THL

3.0 3.3 3.6

OUTPUT LOW VOLTAGE

vs. SUPPLY VOLTAGE

MAX9121/22 toc07

SUPPLY VOLTAGE (V)

OUTPUT LOW VOLTAGE (mV)

100

1.60

1.80

1.70

2.00

1.90

2.10

2.20

3.0 3.3 3.6

DIFFERENTIAL PROPAGATION DELAY

vs. SUPPLY VOLTAGE

MAX9121/22 toc08

SUPPLY VOLTAGE (V)

DIFFERENTIAL PROPAGATION DELAY (ns)

PHLD

PLHD

1.50

1.70

1.90

2.10

-40 10-15 35 60 85

DIFFERENTIAL PROPAGATION DELAY

vs. TEMPERATURE

MAX9121/22 toc09

TEMPERATURE (°C)

DIFFERENTIAL PROPAGATION DELAY (ns)

PHLD

PLHD

1.25

1.50

2.00

1.75

2.25

2.50

-0.5 0.50 1.0 1.5 2.0 2.5

DIFFERENTIAL PROPAGATION DELAY

vs. COMMON-MODE VOLTAGE

MAX9121/22 toc10

COMMON-MODE VOLTAGE (V)

DIFFERENTIAL PROPAGATION DELAY (ns)

PHLD

PLHD

1.5

1.7

1.6

1.9

1.8

2.1

2.0

2.2

100 900 1700 2500

DIFFERENTIAL PROPAGATION DELAY

vs. DIFFERENTIAL INPUT VOLTAGE

MAX9121/22 toc11

DIFFERENTIAL INPUT VOLTAGE (mV)

DIFFERENTIAL PROPAGATION DELAY (ns)

PHLD

PLHD

200

175

150

125

100

3.0 3.3 3.6

DIFFERENTIAL PULSE SKEW vs.

SUPPLY VOLTAGE

MAX9121/22 toc12

SUPPLY VOLTAGE (V)

DIFFERENTIAL PULSE SKEW (ps)

MAX9121/MAX9122

Quad LVDS Line Receivers with

Integrated Termination and Flow-Through Pinout

6 _______________________________________________________________________________________

Detailed Description

The LVDS interface standard is a signaling method

intended for point-to-point communication over a con-

trolled-impedance medium as defined by the ANSI

TIA/EIA-644 and IEEE 1596.3 standards. The LVDS stan-

dard uses a lower voltage swing than other common

communication standards, achieving higher data rates

with reduced power consumption while reducing EMI

emissions and system susceptibility to noise.

The MAX9121/MAX9122 are 500Mbps, four-channel

LVDS receivers intended for high-speed, point-to-point,

low-power applications. Each channel accepts an

LVDS input and translates it to an LVTTL/LVCMOS out-

put. The receiver is capable of detecting differential

signals as low as 100mV and as high as 1V within an

input voltage range of 0 to 2.4V. The 250mV to 400mV

differential output of an LVDS driver is nominally cen-

tered around a +1.2V offset. This offset, coupled with

the receiver’s 0 to 2.4V input voltage range, allows an

approximate ±1V shift in the signal (as seen by the

receiver). This allows for a difference in ground refer-

ences of the transmitter and the receiver, the common-

mode effects of coupled noise, or both. The LVDS stan-

dards specify an input voltage range of 0 to +2.4V

referenced to receiver ground.

The MAX9122 has an integrated termination resistor

that is internally connected across each receiver input.

The internal termination saves board space, eases lay-

out, and reduces stub length compared to an external

termination resistor. In other words, the transmission

line is terminated on the IC.

Fail-Safe

The fail-safe feature of the MAX9121/MAX9122 sets an

output high when:

• Inputs are open.

• Inputs are undriven and shorted.

• Inputs are undriven and terminated.

A fail-safe circuit is important because under these

conditions, noise at the inputs may switch the receiver

and it may appear to the system that data is being

Pin Description

PIN NAME FUNCTION

1, 4, 5, 8 IN_- Inverting Differential Receiver Inputs

2, 3, 6, 7 IN_+ Noninverting Differential Receiver Inputs

9, 16 EN, EN

Receiver Enable Inputs. When EN = high and EN = low or open, the outputs are active. For

other combinations of EN and EN, the outputs are disabled and in high impedance.

10, 11, 14, 15 OUT_ LVCMOS/LVTTL Receiver Outputs

12 GND Ground

13 V

Power-Supply Input. Bypass V

to GND with 0.1µF and 0.001µF ceramic capacitors.

Table 1. Input/Output Function Table

ENABLES INPUTS OUTPUT

EN EN (IN_+) - (IN_-) OUT_

≥ +100mV H

≤ -100mV L

MAX9121

Open, undriven short, or undriven

100Ω parallel termination

H L or open

MAX9122 Open or undriven short

All other combinations of ENABLE pins Don’t care Z

P1-P3 P4-P6 P7-P9 P10-P12

MAX9122EUE+T

Mfr. #:

Buy MAX9122EUE+T

Manufacturer:

Maxim Integrated

Description:

LVDS Interface IC Quad LVDS Line Receiver

Lifecycle:

New from this manufacturer.

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MAX9122EUE+T

MAX9122EUE+T

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