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MAX9122EUE+T

P1-P3P4-P6P7-P9P10-P12
received. Open or undriven terminated input conditions
can occur when a cable is disconnected or cut, or
when the LVDS driver outputs are high impedance. A
short condition can occur because of a cable failure.
The fail-safe input network (Figure 1) samples the input
common-mode voltage and compares it to V
CC
- 0.3V
(nominal). When the input is driven to levels specified in
the LVDS standards, the input to the common-mode
voltage is less than V
CC
- 0.3V and the fail-safe circuit
is not activated. If the inputs are open or if the inputs
are undriven and shorted or undriven and parallel ter-
minated, there is no input current. In this case, a pullup
resistor in the fail-safe circuit pulls both inputs above
V
CC
- 0.3V, activating the fail-safe circuit and forcing
the output high.
Applications Information
Power-Supply Bypassing
Bypass the V
CC
pin with high-frequency surface-mount
ceramic 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible, with the smaller valued
capacitor closest to V
CC
.
Differential Traces
Input trace characteristics affect the performance of the
MAX9121/MAX9122. Use controlled-impedance PC
board traces to match the cable characteristic imped-
ance. The termination resistor is also matched to this
characteristic impedance.
Eliminate reflections and ensure that noise couples as
common mode by running the differential traces close
together. Reduce skew by matching the electrical
length of the traces. Excessive skew can result in a
degradation of magnetic field cancellation.
Each channel’s differential signals should be routed
close to each other to cancel their external magnetic
field. Maintain a constant distance between the differ-
ential traces to avoid discontinuities in differential
impedance. Avoid 90° turns and minimize the number
of vias to further prevent impedance discontinuities.
MAX9121/MAX9122
Quad LVDS Line Receivers with
Integrated Termination and Flow-Through Pinout
_______________________________________________________________________________________ 7
IN_+
V
CC
- 0.3V
IN_-
OUT_
MAX9121 MAX9122
R
IN2
V
CC
R
IN1
R
IN1
IN_+
V
CC
- 0.3V
IN_-
OUT_
R
IN2
V
CC
R
IN1
R
DIFF
R
IN1
Figure 1. Input with Fail-Safe Network
MAX9121/MAX9122
Quad LVDS Line Receivers with
Integrated Termination and Flow-Through Pinout
8 _______________________________________________________________________________________
Cables and Connectors
Transmission media typically have a controlled differen-
tial impedance of 100Ω. Use cables and connectors
that have matched differential impedance to minimize
impedance discontinuities.
Avoid the use of unbalanced cables such as ribbon or
simple coaxial cable. Balanced cables such as twisted
pair offer superior signal quality and tend to generate
less EMI due to magnetic field canceling effects.
Balanced cables pick up noise as common mode,
which is rejected by the LVDS receiver.
Termination
The MAX9122 has an integrated termination resistor
connected across the inputs of each receiver. The
value of the integrated resistor is specified in the DC
characteristics.
The MAX9121 requires an external termination resistor.
The termination resistor should match the differential
impedance of the transmission line. Termination resis-
tance values may range between 90Ω to 132Ω,
depending on the characteristic impedance of the
transmission medium.
When using the MAX9121, minimize the distance
between the input termination resistors and the
MAX9121 receiver inputs. Use 1% surface-mount resis-
tors.
IN_+
IN_-
OUT_
RECEIVER ENABLED
1/4 MAX9121/MAX9122
50Ω REQUIRED FOR PULSE GENERATOR.
WHEN TESTING THE MAX9122, ADJUST THE
PULSE GENERATOR OUTPUT TO ACCOUNT
FOR INTERNAL TERMINATION RESISTOR.
*
**
PULSE
GENERATOR**
50Ω*50Ω*
C
L
Figure 2. Propagation Delay and Transition Time Test Circuit
Figure 3. Propagation Delay and Transition Time Waveforms
IN_-
IN_+
OUT_
50%
V
ID
V
OL
V
OH
V
ID
= 0
20%20%
80% 80%
t
PHLD
t
PLHD
t
THL
t
TLH
V
ID
= 0
50%
V
ID
= (V
IN_+
) - (V
IN_-
)
NOTE: V
CM
= (V
IN-
+ V
IN+
)
2
Board Layout
Because the MAX9121/MAX9122 feature a flow-through
pinout, no special layout precautions are required.
Keep the LVDS and any other digital signals separated
from each other to reduce crosstalk.
For LVDS applications, a four-layer PC board that pro-
vides separate power, ground, LVDS signals, and input
signals is recommended. Isolate the input LVDS signals
from each other to prevent coupling. Isolate the output
LVCMOS/LVTTL signals from each other to prevent
coupling. Separate the input LVDS signals from the out-
put signals planes with the power and ground planes
for best results.
MAX9121/MAX9122
Quad LVDS Line Receivers with
Integrated Termination and Flow-Through Pinout
_______________________________________________________________________________________ 9
IN_+
EN
EN
IN_-
OUT_
DEVICE
UNDER
TEST
1/4 MAX9121/MAX9122
C
L
INCLUDES LOAD AND TEST JIG CAPACITANCE.
S
1
= V
CC
FOR t
PZL
AND t
PLZ
MEASUREMENTS.
S
1
= GND FOR t
PZH
AND t
PHZ
MEASUREMENTS.
GENERATOR
50Ω
C
L
R
L
S
1
V
CC
Figure 4. High-Impedance Delay Test Circuit
Figure 5. High-Impedance Delay Waveforms
1.5V
EN WHEN EN = GND OR OPEN
EN WHEN EN = V
CC
OUTPUT WHEN
V
ID
= -100mV
OUTPUT WHEN
V
ID
= +100mV
1.5V
1.5V
0.5V
0.5V
t
PLZ
t
PHZ
t
PZL
t
PZH
1.5V
3V
0
3V
V
CC
V
OL
V
OH
GND
0
50%
50%
Chip Information
TRANSISTOR COUNT: 1354
PROCESS: CMOS
P1-P3P4-P6P7-P9P10-P12

MAX9122EUE+T

Mfr. #:
Buy MAX9122EUE+T
Manufacturer:
Maxim Integrated
Description:
LVDS Interface IC Quad LVDS Line Receiver
Lifecycle:
New from this manufacturer.
Delivery:
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