CY28339
Document #: 38-07507 Rev. *A Page 3 of 18
Two-Wire SMBus Control Interface
The two-wire control interface implements a Read/Write slave
only interface according to SMBus specification.
The device will accept data written to the D2 address and data
may read back from address D3. It will not respond to any
other addresses, and previously set control registers are
retained as long as power in maintained on the device.
Serial Control Registers
Following the acknowledge of the Address Byte, two additional
bytes must be sent:
1. “Command code“ byte
2. “Byte count” byte.
Although the data (bits) in the command is considered “don’t
care,” it must be sent and will be acknowledged. After the
Command Code and the Byte Count have been acknowl-
edged, the sequence (Byte 0, Byte 1, and Byte 2) described
below will be valid and acknowledged.
Byte 0: CPU Clock Register
[3,4]
Bit @Pu
p
Name Description
7 0 Spread Spectrum Enable.
0 = Spread Off, 1 = Spread On. This is a Read and Write control bit.
6 0 CPU Clock Power-down Mode Select.
0 = Drive CPUT to 2x IREF and drive CPUC LOW
1 = Tri-state all CPU outputs.
This is only applicable when PD# is LOW. It is not applicable to CPU_STOP#.
5 0 3V66_1/VC
H
3V66_1/VCH Frequency Select
0 = 66M selected, 1 = 48M selected. This is a Read and Write control bit.
4 Reserved
3 HW PCI_STOP# Reflects the current value of the internal PCI_STOP# function when read. Internally PCI_STOP#
is a logical AND function of the internal SMBus register bit and the external PCI_STOP# pin.
2 HW S2 Frequency Select Bit 2. Reflects the value of S2. This bit is Read-only.
1 HW S1 Frequency Select Bit 1. Reflects the value of S1. This bit is Read-only.
01 Reserved
Byte 1: CPU Clock Register
Bit @Pu
p
Name Description
71 Reserved
6 0 CPUT1, CPUC1
CPUT2, CPUC2
CPUT/C Output Functionality Control when CPU_STOP# is asserted.
0 = Drive CPUT to 6x IREF and drive CPUC LOW
1 = three-state all CPU outputs.
This bit will override Byte0,Bit6 such that even if it is 0, when PD# goes LOW the CPU outputs
will be three-stated.
5 0 CPUT2, CPUC2 CPUT/C2 Functionality Control when CPU_STOP# is asserted.
0 = Stopped LOW,1 = Free Running. This is a Read and Write control bit.
4 0 CPUT1, CPUC1 CPUT/C1 Functionality Control When CPU_STOP# is asserted.
0 = Stopped LOW, 1 = Free Running. This is a Read and Write control bit.
30 Reserved
2 1 CPUT2, CPUC2 CPUT/C2 Output Control.
0 = disable, 1 = enabled. This is a Read and Write control bit.
1 1 CPUT1, CPUC1 CPUT/C1 Output Control.
0 = disable, 1 = enabled. This is a Read and Write control bit.
01 Reserved
Notes:
3. PU = internal pull-up. PD = internal pull-down. T = tri-level logic input with valid logic voltages of LOW = < 0.8V, T = 1.0 – 1.8V and HIGH = > 2.0V.
4. The “Pin#” column lists the relevant pin number where applicable. The “@Pup” column gives the default state at power-up.
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