AD670JN Datasheet AD670JNZ, AD670SE/883B, AD670KPZ | P10-P12

AD670

REV. A

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APPLYING THE AD670

The AD670 has been designed for ease of use, system compat-

ibility, and minimization of external components. Transducer

interfaces generally require signal conditioning and preampli-

fication before the signal can be converted. The AD670 will

reduce and even eliminate this excess circuitry in many cases.

To illustrate the flexibility and superior solution that the AD670

can bring to a transducer interface problem, the following dis-

cussions are offered.

Temperature Measurements

Temperature transducers are one of the most common sources

of analog signals in data acquisition systems. These sensors re-

quire circuitry for excitation and preamplification/buffering. The

instrumentation amplifier input of the AD670 eliminates the

need for this signal conditioning. The output signals from tem-

perature transducers are generally sufficiency slow that a

sample/hold amplifier is not required. Figure 12 shows tile

AD590 IC temperature transducer interfaced to the AD670.

The AD580 voltage reference is used to offset the input for 0°C

calibration. The current output of the AD590 is converted into

a voltage by R1. The high impedance unbuffered voltage is ap-

plied directly to the AD670 configured in the –128 mV to

127 mV bipolar range. The digital output will have a resolution

of 1°C.

Figure 12. AD670 Temperature Transducer lnterface

Platinum RTDs are also a popular, temperature transducer.

Typical RTDs have a resistance of 100 Ω at 0°C and change re-

sistance 0.4 Ω per °C. If a consent excitation current is caused

to flow in the RTD, the change in voltage drop will be a mea-

sure of the change in temperature. Figure 13 shows such a

method and the required connections to the AD670. The

AD580 2.5 V reference provides the accurate voltage for the ex-

citation current and range offsetting for the RTD. The op amp

is configured to force a constant 2.5 mA current through the

RTD. The differential inputs of the AD670 measure the differ-

ence between a fixed offset voltage and the temperature depen-

dent output of the op amp which varies with the resistance of

the RTD. The RTD change of approximately 0.4 Ω/°C results

in a 1 mV/°C voltage change. With the AD670 in the 1 mV/LSB

range, temperatures from 0°C to 255°C can be measured.

Figure 13. Low Cost RTD Interface

Differential temperature measurements can be made using an

AD590 connected to each of the inputs as shown in Figure 14.

This configuration will allow the user to measure the relative

temperature difference between two points with a 1°C resolu-

tion. Although the internal 1k and 9k resistors on the inputs

have ±20% tolerance, trimming the AD590 is unnecessary as

most differential temperature applications are concerned with

the relative differences between the two. However, the user may

see up to a 20% scale factor error in the differential temperature

to digital output transfer curve.

This scale factor error can be eliminated through a software cor-

rection. Offset corrections can be made by adjusting for any dif-

ference that results when both sensors are held at the same

temperature. A span adjustment can then be made by immers-

ing one AD590 in an ice bath and one in boiling water and

eliminating any deviation from 100°C. For a low cost version of

this setup, the plastic AD592 can be substituted for the AD590.

Figure 14. Differential Temperature Measurement

Using the AD590

AD670

REV. A

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STRAIN GAGE MEASUREMENTS

Many semiconductor-type strain gages, pressure transducers,

and load cells may also be connected directly to the AD670.

These types of transducers typically produce 30 mV full-scale

per volt of excitation. In the circuit shown in Figure 15, the

AD670 is connected directly to a Data Instruments model JP-20

load cell. The AD584 programmable voltage reference is used

along with an AD741 op amp to provide the ±2.5 V excitation

for the load cell. The output of the transducer will be ±150 mV

for a force of ±20 pounds. The AD670 is configured for the

±128 millivolt range. The resolution is then approximately 2.1

ounces per LSB over a range of ±17 pounds. Scaling to exactly

2 ounces per LSB can be accomplished by trimming the refer-

ence voltage which excites the load cell.

Figure 15. AD670 Load Cell Interface

MULTIPLEXED INPUTS

Most data acquisition systems require the measurement of sev-

eral analog signals. Multiple A/D converters are often used to

digitize these inputs, requiring additional preamplification and

buffer stages per channel. Since these signals vary slowly, a dif-

ferential MUX can multiplex inputs from several transducers

into a single AD670. And since the AD670’s signal-conditioning

capability is preserved, the cost of several ADCs, differential

amplifiers, and other support components can be reduced to

that of a single AD670, a MUX, and a few digital logic gates.

An AD7502 dual 4-channel MUX appears in Figure 16 multi-

plexing four differential signals to the AD670. The AD7502’s

decoded address is gated with the microprocessor’s write signal

to provide a latching strobe at the flip-flops. A write cycle to the

AD7502’s address then latches the two LSBs of the data word

thereby selecting the input channel for subsequent conversions.

Figure 16. Multiplexed Analog Inputs to AD670

SAMPLED INPUTS

For those applications where the input signal is capable of slew-

ing more than 1/2 LSB during the AD670’s 10 µs conversion

cycle, the input should be held constant for the cycle’s duration.

The circuit shown in Figure 17 uses a CMOS switch and two

capacitors to sample/hold the input. The AD670’s STATUS

output, once inverted, supplies the sample/hold (S/

H) signal.

A convert command applied on the

CE, CS or R/W lines will

initiate the conversion. The AD670’s STATUS output, once in-

verted, supplies the sample/hold signal to the CD4066. The

CD4066 CMOS switch shown in Figure 17 was chosen for its

fast transition times, low on-resistance and low cost. The con-

trol input’s propagation delay for switch-closed to switch-open

should remain less than 150 ns to ensure that the sample-to-

hold transition occurs before the first bit decision in the AD670.

AD670

REV. A

–11–

Figure 17. Low Cost Sample-and-Hold Circuit for AD670

Since settling to 1/2 LSB at 8-bits of resolution requires 6.2 RC

time constants, the 500 pF hold capacitors and CD4066’s 300 Ω

on-resistance yield an acquisition time of under 1 µs, assuming a

low impedance source.

This sample/hold approach makes use of the differential capa-

bilities of the AD670. Because 500 pF hold capacitors are used

on both V

+ and V

– inputs, the droop rate depends only on

the offset current of the AD670, typically 20 nA. With the

matched 500 pF capacitors, the droop rate is 40 µV/µs. The in-

put will then droop only 0.4 mV (0.4 LSB) during the AD670’s

10 µs conversion time. The differential approach also minimizes

pedestal error since only the difference in charge injection be-

tween the two switches results in errors at the A/D.

The fast conversion time and differential and common-mode ca-

pabilities of the AD670 permit this simple sample-hold design

to perform well with low sample-to-hold offset, droop rate of

about 40 µV/µs and acquisition time under 1 µs. The effective

aperture time of the AD670 is reduced by about 2 orders of

magnitude with this circuit, allowing frequencies to be con-

verted up to several kilohertz.

While no input anti-aliasing filter is shown, filtering will be nec-

essary to prevent output errors if higher frequencies are present

in the input signal. Many practical variations are possible with

this circuit, including input MUX control, for digitizing a num-

ber of ac channels.

IBM PC INTERFACE

The AD670 appears in Figure 18 interfaced to the IBM PC.

Since the device resides in I/O space, its address is decoded

from only the lower ten address lines and must be gated with

AEN (active low) to mask out internal (DMA) cycles which use

the same I/O address space. This active low signal is applied to

CS. AO, meanwhile, is reserved for the R/W input. This places

the AD670 in two adjacent addresses; one for starting the con-

version and the other for reading the result. The

IOR and IOW

signals are then gated and applied to

CE, while the lower two

data lines are applied to FORMAT and BPO/

UPO inputs to

provide software programmable input formats and output

coding.

In BASIC, a simple OUT ADDR, WORD command initiates a

conversion. While the upper six bits of the data WORD are

meaningless, the lower two bits define the analog input format

and digital output coding according to Table IV. The data is

available ten microseconds later (which is negligible in BASIC)

and can be read using INP (ADDR + 1). The 3-line subroutine

in Figure 19, used in conjunction with the interface of Figure

18, converts an analog input within a bipolar range to an offset

binary coded digital word.

Figure 18. IBM PC lnterface to AD670

NOTE: Due to the large number of options that may be in-

stalled in the PC, the I/O bus loading should be limited to one

Schottky TTL load. Therefore, a buffer/driver should be used

when interfacing more than two AD670s to the I/O bus.

Table IV.

Data Input Format Output Coding

0 Unipolar Straight Binary

1 Bipolar Offset Binary

2 Unipolar 2s Complement

3 Bipolar 2s Complement

10 OUT & H310,1 ’INITIATE CONVERSION

20 ANALOGIN = INP (&H311) ’READ ANALOG INPUT

30 RETURN

Figure 19. Conversion Subroutine

P1-P3 P4-P6 P7-P9 P10-P12 P13-P13

AD670JN

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Description:

IC ADC 8BIT SGNL COND 20-DIP

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AD670JN

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