AD670JN Datasheet AD670JNZ, AD670SE/883B, AD670KPZ | P7-P9

AD670

REV. A

–6–

Table I. AD670 Input Selection/Output Format Truth Table

INPUT RANGE/

BPO/

UPO

FORMAT OUTPUT FORMAT

0 0 Unipolar/Straight Binary

1 0 Bipolar/Offset Binary

0 1 Unipolar/2s Complement

1 1 Bipolar/2s Complement

DIFF STRAIGHT BINARY

–V

(FORMAT = 0, BPO/UPO = 0)

0 0 0 0000 0000

128 mV 0 128 mV 1000 0000

255 mV 0 255 mV 1111 1111

255 mV 255 mV 0 0000 0000

128 mV 127 mV 1 mV 0000 0001

128 mV –127 mV 255 mV 1111 1111

Figure 5a. Unipolar Output Codes (Low Range)

OFFSET BINARY 2s COMPLEMENT

DIFF (FORMAT = 0, (FORMAT = 1,

–V

BPO/UPO = 1) BPO/UPO = 1)

0 0 0 1000 0000 0000 0000

127 mV 0 127 mV 1111 1111 0111 1111

1.127 V 1.000 V 127 mV 1111 1111 0111 1111

255 mV 255 mV 0 1000 0000 0000 0000

128 mV 127 mV 1 mV 1000 0001 0000 0001

127 mV 128 mV –1 mV 0111 1111 1111 1111

127 mV 255 mV –128 mV 0000 0000 1000 0000

–128 mV 0 –128 mV 0000 0000 1000 0000

Figure 5b. Bipolar Output Codes (Low Range)

Calibration

Because of its precise factory calibration, the AD670 is intended

to be operated without user trims for gun and offset; therefore,

no provisions have been made for such user trims. Figures 6a,

6b, and 6c show the transfer curves at zero and full scale for the

unipolar and bipolar modes. The code transitions are positioned

so that the desired value is centered at that code. The first LSB

transition for the unipolar mode occurs for an input of +1/2 LSB

(5 mV or 0.5 mV). Similarly, the MSB transition for the bipolar

mode is set at –1/2 LSB (–5 mV or –0.5 mV). The full scale

transition is located at the full scale value –1 1/2 LSB. These

values are 2.545 V and 254.5 mV.

6a. Unipolar Transfer Curve

Figure 4a. CMRR Over Frequency

Figure 4b. AD670 Input Rejects Common-Mode

Ground Noise

Good common-mode performance is useful in a number of situ-

ations. In bridge-type transducer applications, such performance

facilitates the recovery of differential analog signals in the pres-

ence of a dc common-mode or a noisy electrical environment.

High frequency CMRR also becomes important when the ana-

log signal is referred to a noisy, remote digital ground. In each

case, the CMRR specification of the AD670 allows the integrity

of the input signal to be preserved.

The AD670’s common-mode voltage tolerance allows great

flexibility in circuit layout. Most other A/D converters require

the establishment of one point as the analog reference point.

This is necessary in order to minimize the effects of parasitic

voltages. The AD670, however, eliminates the need to make the

analog ground reference point and A/D analog ground one and

the same. Instead, a system such as that shown in Figure 4b is

possible as a result of the AD670’s common-mode performance.

The resistors and inductors in the ground return represent un-

avoidable system parasitic impedances.

Input/Output Options

Data output coding (2s complement vs. straight binary) is

selected using Pin 12, the FORMAT pin. The selection of

input format (bipolar vs. unipolar) is controlled using Pin 11,

BPO/

UPO. Prior to a write/convert, the state of FORMAT and

BPO/

UPO should be available to the converter. These lines may

be tied to the data bus and may be changed with each conver-

sion if desired. The configurations are shown in Table I. Output

coding for representative signals in each of these configurations

is shown in Figure 5.

An output signal, STATUS, indicates the status of the conver-

sion. STATUS goes high at the beginning of the conversion and

returns low when the conversion cycle has been completed.

AD670

REV. A

–7–

Table III. AD670 TIMING SPECIFICATIONS

@ +258C

Symbol Parameter Min Typ Max Units

WRITE/CONVERT START MODE

Write/Start Pulse Width 300 ns

Input Data Setup Time 200 ns

Input Data Hold 10 ns

RWC

Read/Write Setup Before Control 0 ns

Delay to Convert Start 700 ns

Conversion Time 10 µs

READ MODE

Read Time 250 ns

Delay from Status Low to Data Read 250 ns

Bus Access Time 200 250 ns

Data Hold Time 25 ns

Output Float Delay 150 ns

R/W before CE or CS low 0 ns

Boldface indicates parameters tested 100% unless otherwise noted. See Specifications page for explanation.

6b. Bipolar

6c. Full Scale (Unipolar)

Figure 6. Transfer Curves

CONTROL AND TIMING OF THE AD670

Control Logic

The AD670 contains on-chip logic to provide conversion and

data read operations from signals commonly available in micro-

processor systems. Figure 7 shows the internal logic circuitry of

the AD670. The control signals,

CE, CS, and R/W control the

operation of the converter. The read or write function is deter-

mined by R/

W when both CS and CE are low as shown in

Table II. If all three control inputs are held low longer than the

conversion time, the device will continuously convert until one

input,

CE, CS, or R/W is brought high. The relative timing of

these signals is discussed later in this section.

Figure 7. Control Logic Block Diagram

Table II. AD670 Control Signal Truth Table

R/W CS CE OPERATION

0 0 0 WRITE/CONVERT

1 0 0 READ

X X 1 NONE

X 1 X NONE

Timing

The AD670 is easily interfaced to a variety of microprocessors

and other digital systems. The following discussion of the timing

requirements of the AD670 control signals will provide the de-

signer with useful insight into the operation of the device.

Write/Convert Start Cycle

Figure 8 shows a complete timing diagram for the write/convert

start cycle.

CS (chip select) and CE (chip enable) are active low

and are interchangeable signals. Both

CS and CE must be low

for the converter to read or start a conversion. The minimum

pulse width, t

, on either CS or CE is 300 ns to start a

conversion.

AD670

REV. A

–8–

Figure 8. Write/Convert Start Timing

The R/W line is used to direct the converter to start a conver-

sion (R/

W low) or read data (R/W high). The relative sequenc-

ing of the three control signals (R/

W, CE, CS) is unimportant.

However, when all three signals remain low for at least 300 ns

), STATUS will go high to signal that a conversion is taking

place.

Once a conversion is started and the STATUS line goes high,

convert start commands will be ignored until the conversion

cycle is complete. The output data buffer cannot be enabled

during a conversion.

Read Cycle

Figure 9 shows the timing for the data read operation. The data

outputs are in a high impedance state until a read cycle is initi-

ated. To begin the read cycle, R/

W is brought high. During a

read cycle, the minimum pulse length for

CE and CS is a func-

tion of the length of time required for the output data to be

valid. The data becomes valid and is available to the data bus in

a maximum of 250 ns. This delay between the high impedance

state and valid data is the maximum bus access time or t

Bringing

CE or CS high during valid data ends the read cycle.

The outputs remain valid for a minimum of 25 ns (t

) and re-

turn to the high impedance state after a delay, t

, of 150 ns

maximum.

Figure 9. Read Cycle Timing

STAND-ALONE OPERATION

The AD670 can be used in a “stand-alone” mode, which is use-

ful in systems with dedicated input ports available. Two typical

conditions are described and illustrated by the timing diagrams

which follow.

Single Conversion, Single Read

When the AD670 is used in a stand-alone mode, CS and CE

should be tied together. Conversion will be initiated by bringing

W low. Within 700 ns, a conversion will begin. The R/W

pulse should be brought high again once the conversion has

started so that the data will be valid upon completion of the

conversion. Data will remain valid until

CE and CS are brought

high to indicate the end of the read cycle or R/

W goes low. The

timing diagram is shown in Figure 10.

Figure 10. Stand-Alone Mode Single Conversion/

Single Read

Continuous Conversion, Single Read

A variety of applications may call for the A/D to be read after

several conversions. In process control systems, this is often the

case since a reading from a sensor may only need to be updated

every few conversions. Figure 11 shows the timing relationships.

Once again,

CE and CS should be tied together. Conversion

will begin when the R/

W signal is brought low. The device will

convert repeatedly as indicated by the status line. A final con-

version will take place once the R/

W line has been brought high.

The rising edge of R/

W must occur while STATUS is high. R/W

should not return high while STATUS is low since the circuit is

in a reset state prior to the next conversion. Since the rising

edge of R/

W must occur while STATUS is high, R/W’s length

must be a minimum of 10.25 µs (t

+ t

). Data becomes valid

upon completion of the conversion and will remain so until the

CE and CS lines are brought high indicating the end of the read

cycle or R/

W goes low initiating a new series of conversions.

Figure 11. Stand-Alone Mode Continuous Conversion/

Single Read

P1-P3 P4-P6 P7-P9 P10-P12 P13-P13

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