10
82C54
the counters selected by setting their corresponding bits D3,
D2, D1 = 1.
The read-back command may be used to latch multiple
counter output latches (OL) by setting the COUNT bit D5 = 0
and selecting the desired counter(s). This signal command is
functionally equivalent to several counter latch commands,
one for each counter latched. Each counter’s latched count
is held until it is read (or the counter is reprogrammed). That
counter is automatically unlatched when read, but other
counters remain latched until they are read. If multiple count
read-back commands are issued to the same counter
without reading the count, all but the first are ignored; i.e.,
the count which will be read is the count at the time the first
read-back command was issued.
The read-back command may also be used to latch status
information of selected counter(s) by setting STATUS bit D4
= 0. Status must be latched to be read; status of a counter is
accessed by a read from that counter.
The counter status format is shown in Figure 6. Bits D5
through D0 contain the counter’s programmed Mode exactly
as written in the last Mode Control Word. OUTPUT bit D7
contains the current state of the OUT pin. This allows the
user to monitor the counter’s output via software, possibly
eliminating some hardware from a system.
NULL COUNT bit D6 indicates when the last count written to
the counter register (CR) has been loaded into the counting
element (CE). The exact time this happens depends on the
Mode of the counter and is described in the Mode Definitions,
but until the counter is loaded into the counting element (CE),
it can’t be read from the counter. If the count is latched or read
before this time, the count value will not reflect the new count
just written. The operation of Null Count is shown below.
THIS ACTION: CAUSES:
A. Write to the control word register:(1) . . . . Null Count = 1
B. Write to the count register (CR):(2). . . . . . Null Count = 1
C. New count is loaded into CE (CR - CE) . . Null Count = 0
1. Only the counter specified by the control word will have
its null count set to 1. Null count bits of other counters are
unaffected.
2. If the counter is programmed for two-byte counts (least
significant byte then most significant byte) null count goes
to 1 when the second byte is written.
If multiple status latch operations of the counter(s) are
performed without reading the status, all but the first are
ignored; i.e., the status that will be read is the status of the
counter at the time the first status read-back command was
issued.
Both count and status of the selected counter(s) may be
latched simultaneously by setting both COUNT and STATUS
bits D5, D4 = 0. This is functionally the same as issuing two
separate read-back commands at once, and the above
discussions apply here also. Specifically, if multiple count
and/or status read-back commands are issued to the same
counter(s) without any intervening reads, all but the first are
ignored. This is illustrated in Figure 7.
If both count and status of a counter are latched, the first
read operation of that counter will return latched status,
regardless of which was latched first. The next one or two
reads (depending on whether the counter is programmed for
one or two type counts) return latched count. Subsequent
reads return unlatched count.
A0, A1 = 11; CS
= 0; RD = 1; WR = 0
D7 D6 D5 D4 D3 D2 D1 D0
1 1 COUNT
STATUS CNT 2 CNT 1 CNT 0 0
D5:0=Latch count of selected Counter (s)
D4:0=Latch status of selected Counter(s)
D3:1=Select Counter 2
D2:1=Select Counter 1
D1:1=Select Counter 0
D0:Reserved for future expansion; Must be 0
FIGURE 5. READ-BACK COMMAND FORMAT
D7 D6 D5 D4 D3 D2 D1 D0
OUTPUT NULL
COUNT
RW1 RW0 M2 M1 M0 BCD
D7:1=Out pin is 1
0=Out pin is 0
D6:1=Null count
0=Count available for reading
D5-D0=Counter programmed mode (See Control Word Formats)
FIGURE 6. STATUS BYTE
11
82C54
MODE DEFINITIONS
The following are defined for use in describing the operation
of the 82C54.
CLK PULSE - A rising edge, then a falling edge, in that
order, of a Counter’s CLK input.
TRIGGER - A rising edge of a Counter’s Gate input.
COUNTER LOADING - The transfer of a count from the CR
to the CE (See “Functional Description”)
MODE 0: INTERRUPT ON TERMINAL COUNT
Mode 0 is typically used for event counting. After the Control
Word is written, OUT is initially low, and will remain low until
the Counter reaches zero. OUT then goes high and remains
high until a new count or a new Mode 0 Control Word is
written to the Counter.
GATE = 1 enables counting; GATE = 0 disables counting.
GATE has no effect on OUT.
After the Control Word and initial count are written to a
Counter, the initial count will be loaded on the next CLK
pulse. This CLK pulse does not decrement the count, so for
an initial count of N, OUT does not go high until N + 1 CLK
pulses after the initial count is written.
If a new count is written to the Counter it will be loaded on
the next CLK pulse and counting will continue from the new
count. If a two-byte count is written, the following happens:
1. Writing the first byte disables counting. Out is set low
immediately (no clock pulse required).
2. Writing the second byte allows the new count to be
loaded on the next CLK pulse.
This allows the counting sequence to be synchronized by
software. Again OUT does not go high until N + 1 CLK
pulses after the new count of N is written.
COMMANDS
DESCRIPTION RESULTD7 D6 D5 D4 D3 D2 D1 D0
1 1 0 0 0 0 1 0 Read-Back Count and Status of Counter 0 Count and Status Latched for Counter 0
1 1 1 0 0 1 0 0 Read-Back Status of Counter 1 Status Latched for Counter 1
1 1 1 0 1 1 0 0 Read-Back Status of Counters 2, 1 Status Latched for Counter 2,
But Not Counter 1
1 1 0 1 1 0 0 0 Read-Back Count of Counter 2 Count Latched for Counter 2
1 1 0 0 0 1 0 0 Read-Back Count and Status of Counter 1 Count Latched for Counter 1,
But Not Status
1 1 1 0 0 0 1 0 Read-Back Status of Counter 1 Command Ignored, Status Already
Latched for Counter 1
FIGURE 7. READ-BACK COMMAND EXAMPLE
CS RD WR A1 A0
01000Write into Counter 0
01001Write into Counter 1
01010Write into Counter 2
01011Write Control Word
00100Read from Counter 0
00101Read from Counter 1
00110Read from Counter 2
00111No-Operation (Three-State)
1XXXXNo-Operation (Three-State)
0 1 1 X X No-Operation (Three-State)
FIGURE 8. READ/WRITE OPERATIONS SUMMARY
12
82C54
If an initial count is written while GATE = 0, it will still be
loaded on the next CLK pulse. When GATE goes high, OUT
will go high N CLK pulses later; no CLK pulse is needed to
load the counter as this has already been done.
NOTES: The following conventions apply to all mode timing diagrams.
1. Counters are programmed for binary (not BCD) counting and for
reading/writing least significant byte (LSB) only.
2. The counter is always selected (CS
always low).
3. CW stands for “Control Word”; CW = 10 means a control word of
10, Hex is written to the counter.
4. LSB stands for Least significant “byte” of count.
5. Numbers below diagrams are count values. The lower number is
the least significant byte. The upper number is the most
significant byte. Since the counter is programmed to read/write
LSB only, the most significant byte cannot be read.
6. N stands for an undefined count.
7. Vertical lines show transitions between count values.
MODE 1: HARDWARE RETRIGGERABLE ONE-SHOT
OUT will be initially high. OUT will go low on the CLK pulse
following a trigger to begin the one-shot pulse, and will remain
low until the Counter reaches zero. OUT will then go high and
remain high until the CLK pulse after the next trigger.
After writing the Control Word and initial count, the Counter is
armed. A trigger results in loading the Counter and setting
OUT low on the next CLK pulse, thus starting the one-shot
pulse N CLK cycles in duration. The one-shot is retriggerable,
hence OUT will remain low for N CLK pulses after any trigger.
The one-shot pulse can be repeated without rewriting the
same count into the counter. GATE has no effect on OUT.
If a new count is written to the Counter during a one-shot
pulse, the current one-shot is not affected unless the
Counter is retriggerable. In that case, the Counter is loaded
with the new count and the one-shot pulse continues until
the new count expires.
CW = 10 LSB = 4
WR
CLK
GATE
OUT
WR
CLK
GATE
OUT
WR
CLK
GATE
OUT
CW = 10 LSB = 3
CW = 10 LSB = 3
LSB = 2
NNNN
0
4
0
3
0
2
0
1
0
0
FF
FF
FF
FE
NNNN
0
3
0
2
0
2
0
2
0
1
0
0
FF
FF
NNNN
0
3
0
2
0
1
0
2
0
1
0
0
FF
FF
FIGURE 9. MODE 0
WR
CLK
GATE
OUT
WR
CLK
GATE
OUT
WR
CLK
GATE
OUT
NNNN
0
3
0
2
0
1
0
0
FF
FF
0
3
0
2
N
CW = 12 LSB = 3
CW = 12 LSB = 3
CW = 12 LSB = 2
LSB = 4
NNNN
0
2
0
1
0
0
FF
FF
FF
FE
0
4
0
3
N
NNNN
0
3
0
2
0
1
0
3
0
2
0
1
0
0
N
FIGURE 10. MODE 1

CS82C54Z96

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Timers & Support Products PERIPH PRG-CNTR 5V 8MHZ 28PLCC COM
Lifecycle:
New from this manufacturer.
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