LTC3814IFE-5#PBF Datasheet LTC3814IFE-5#PBF, LTC3814EFE-5#TRPBF, LTC3814IFE-5#TRPBF | P10-P12

LTC3814-5

38145fc

OPERATION

Figure 1. Floating TG Driver Supply and Negative BG Return

Main Control Loop

The LTC3814-5 is a current mode controller for DC/DC

step-up converters. In normal operation, the top MOSFET

is turned on for a ﬁ xed interval determined by a one-shot

timer (OST). When the top MOSFET is turned off, the bot-

tom MOSFET is turned on until the current comparator

CMP

trips, restarting the one-shot timer and initiating the

next cycle. Inductor current is determined by sensing the

voltage between the PGND and SW pins using the bottom

MOSFET on-resistance. The voltage on the I

pin sets

the comparator threshold corresponding to the inductor

peak current. The fast 25MHz error ampliﬁ er EA adjusts

this voltage by comparing the feedback signal V

to the

internal 0.8V reference voltage. If the load current increases,

it causes a drop in the feedback voltage relative to the

reference. The I

voltage then rises until the average

inductor current again matches the load current.

The operating frequency is determined implicitly by the

top MOSFET on-time (t

OFF

) and the duty cycle required to

maintain regulation. The one-shot timer generates a top

MOSFET on-time that is inversely proportional to the I

OFF

current and proportional to the V

OFF

voltage. Connecting

OUT

to I

OFF

and V

to V

OFF

with a resistive divider keeps

the frequency approximately constant with changes in V

The nominal frequency can be adjusted with an external

resistor R

OFF

Pulling the RUN/SS pin low forces the controller into its

shutdown state, turning off both M1 and M2. Forcing a

voltage above 0.9V will turn on the device.

Fault Monitoring/Protection

Constant off-time current mode architecture provides ac-

curate cycle-by-cycle current limit protection—a feature

that is very important for protecting the high voltage

power supply from output overcurrent conditions. The

cycle-by-cycle current monitor guarantees that the induc-

tor current will never exceed the value programmed on

the V

RNG

pin.

Overvoltage and undervoltage comparators OV and UV

pull the PGOOD output low if the output feedback voltage

exits a ±10% window around the regulation point after the

internal 125µs power bad mask timer expires. Furthermore,

in an overvoltage condition, M2 is turned off and M1 is

turned on immediately and held on until the overvoltage

condition clears.

The LTC3814-5 provides an undervoltage lockout com-

parator for the INTV

supply. The INTV

UV threshold

is 4.2V to guarantee that the MOSFETs have sufﬁ cient

gate drive voltage before turning on. If INTV

is under

the UV threshold, the LTC3814-5 is shut down and the

drivers are turned off.

Strong Gate Drivers

The LTC3814-5 contains very low impedance drivers ca-

pable of supplying amps of current to slew large MOSFET

gates quickly. This minimizes transition losses and allows

paralleling MOSFETs for higher current applications. A

60V ﬂ oating high side driver drives the topside MOSFET

and a low side driver drives the bottom side MOSFET

(see Figure 1). The bottom side driver is supplied directly

from the INTV

pin. The top MOSFET drivers are biased

from ﬂ oating bootstrap capacitor C

, which normally is

recharged during each off cycle through an external diode

from INTV

when the top MOSFET turns off. In an output

overvoltage condition, where it is possible that the bot-

tom MOSFET will be off for an extended period of time,

an internal timeout guarantees that the bottom MOSFET

is turned on at least once every 25µs for one top MOSFET

on-time period to refresh the bootstrap capacitor.

BOOST

PGND

INTV

LTC3814-5

OUT

38145 F01

LTC3814-5

38145fc

The basic LTC3814-5 application circuit is shown on the

ﬁ rst page of this data sheet. External component selection

is primarily determined by the maximum input voltage and

load current and begins with the selection of the power

MOSFET switches. The LTC3814-5 uses the on-resistance

of the synchronous power MOSFET for determining the

inductor current. The desired amount of ripple current and

operating frequency largely determines the inductor value.

Next, C

OUT

is selected for its ability to handle the large RMS

current and is chosen with low enough ESR to meet the

output voltage ripple and transient speciﬁ cation. Finally,

loop compensation components are selected to meet the

required transient/phase margin speciﬁ cations.

Duty Cycle Considerations

For a boost converter, the duty cycle of the main switch

is:

D= 1−

OUT

MAX

=1−

IN(MIN)

OUT

The maximum V

OUT

capability of the LTC3814-5 is inversely

proportional to the minimum desired operating frequency

and minimum off-time:

OUT(MAX)

IN(MIN)

MIN

•t

OFF(MIN)

≤60V

Maximum Sense Voltage and the V

RNG

The control circuit in the LTC3814-5 measures the input

current by using the R

DS(ON)

of the bottom MOSFET or

by using a sense resistor in the bottom MOSFET source,

so the output current needs to be reﬂ ected back to the

OPERATION

input in order to dimension the power MOSFET properly

and to choose the maximum sense voltage. Based on the

fact that, ideally, the output power is equal to the input

power, the maximum average input current and average

inductor current is:

IN(MAX)

L,AVG(MAX)

O(MAX)

1−D

MAX

The current mode control loop will not allow the induc-

tor peak to exceed V

SENSE(MAX)

SENSE

. In practice, one

should allow some margin for variations in the LTC3814-

5 and external component values, and a good guide for

selecting the maximum sense voltage when V

sensing

is used is:

SENSE(MAX)

1.7 •R

DS(ON)

•I

O(MAX)

1−D

MAX

SENSE

is set by the voltage applied to the V

RNG

pin. Once

SENSE

is chosen, the required V

RNG

voltage is calculated

to be:

RNG

= 5.78 • (V

SENSE(MAX)

+ 0.026)

An external resistive divider from INTV

can be used

to set the voltage of the V

RNG

pin between 0.5V and 2V

resulting in nominal sense voltages of 60mV to 320mV.

Additionally, the V

RNG

pin can be tied to SGND or INTV

in which case the nominal sense voltage defaults to 95mV

or 215mV, respectively.

IC/Driver Supply Power

The LTC3814-5’s internal control circuitry and top and bot-

tom MOSFET drivers operate from a supply voltage (INTV

pin) in the range of 4.5V to 14V. If the input supply voltage

or another available supply is within this voltage range it

can be used to supply IC/driver power. If a supply in this

range is not available, two internal regulators are available

to generate a 5.5V supply from the input or output. An

internal low dropout regulator is good for voltages up to

15V, and the second, a linear regulator controller, controls

the gate of an external NMOS to generate the 5.5V supply.

Since the NMOS is external, the user has the ﬂ exibility to

choose a BV

DSS

as high as necessary.

APPLICATIONS INFORMATION

LTC3814-5

38145fc

Power MOSFET Selection

The LTC3814-5 requires two external N-channel power

MOSFETs, one for the bottom (main) switch and one for

the top (synchronous) switch. Important parameters for

the power MOSFETs are the breakdown voltage BV

DSS

threshold voltage V

(GS)TH

, on-resistance R

DS(ON)

, Miller

capacitance and maximum current I

DS(MAX)

Since the bottom MOSFET is used as the current sense

element, particular attention must be paid to its on-resis-

tance. MOSFET on-resistance is typically speciﬁ ed with

a maximum value R

DS(ON)(MAX)

at 25°C. In this case,

additional margin is required to accommodate the rise in

MOSFET on-resistance with temperature:

DS(ON)(MAX)

SENSE

The ρ

term is a normalization factor (unity at 25°C)

accounting for the signiﬁ cant variation in on-resistance

with

temperature (see Figure 2) and typically varies

from 0.4%/

C to 1.0%/

C depending on the particular

MOSFET used.

ing its off-time and must be chosen with the appropriate

breakdown speciﬁ cation. The LTC3814-5 is designed to

be used with a 4.5V to 14V gate drive supply (INTV

pin)

for driving logic-level MOSFETs (V

GS(MIN)

≥ 4.5V).

For maximum efﬁ ciency, on-resistance R

DS(ON)

and input

capacitance should be minimized. Low R

DS(ON)

minimizes

conduction losses and low input capacitance minimizes

transition losses. MOSFET input capacitance is a combi-

nation of several components but can be taken from the

typical “gate charge” curve included on most data sheets

(Figure 3).

Figure 2. R

DS(ON)

vs Temperature

Figure 3. Gate Charge Characteristic

The curve is generated by forcing a constant input cur-

rent into the gate of a common source, current source

loaded stage and then plotting the gate voltage versus

time. The initial slope is the effect of the gate-to-source

and the gate-to-drain capacitance. The ﬂ at portion of the

curve is the result of the Miller multiplication effect of the

drain-to-gate capacitance as the drain drops the voltage

across the current source load. The upper sloping line is

due to the drain-to-gate accumulation capacitance and

the gate-to-source capacitance. The Miller charge (the

increase in coulombs on the horizontal axis from a to b

while the curve is ﬂ at) is speciﬁ ed for a given V

drain

voltage, but can be adjusted for different V

voltages by

multiplying by the ratio of the application V

to the curve

speciﬁ ed V

values. A way to estimate the C

MILLER

term

is to take the change in gate charge from points a and b

on a manufacturers data sheet and divide by the stated

voltage speciﬁ ed. C

MILLER

is the most important se-

lection criteria for determining the transition loss term in

the top MOSFET but is not directly speciﬁ ed on MOSFET

data sheets. C

RSS

and C

are speciﬁ ed sometimes but

deﬁ nitions of these parameters are not included.

The most important parameter in high voltage applications

is breakdown voltage BV

DSS

. Both the top and bottom

MOSFETs will see full output voltage plus any additional

ringing on the switch node across its drain-to-source dur-

JUNCTION TEMPERATURE (°C)

–50

NORMALIZED ON-RESISTANCE

1.0

1.5

150

38145 F02

0.5

100

2.0

–

OUT

MILLER EFFECT

MILLER

= (Q

– Q

)/V

–

38145 F03

APPLICATIONS INFORMATION

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30

LTC3814IFE-5#PBF

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Description:

Switching Voltage Regulators 60V C Mode Sync Boost Cntr

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