MT9042C Data Sheet
16
Zarlink Semiconductor Inc.
Lock time is very difficult to determine because it is affected by many factors which include:
i) initial input to output phase difference
ii) initial input to output frequency difference
iii) synchronizer loop filter
iv) synchronizer limiter
Although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements.
For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock
time. And better (smaller) phase slope performance (limiter) results in longer lock times. The MT9042C loop filter
and limiter were optimized to meet the AT&T TR62411 jitter transfer and phase slope requirements. Consequently,
phase lock time, which is not a standards requirement, may be longer than in other applications. See AC Electrical
Characteristics - Performance for maximum phase lock time.
MT9042C and Network Specifications
The MT9042C fully meets all applicable PLL requirements (intrinsic jitter, jitter tolerance, jitter transfer, frequency
accuracy, holdover accuracy, capture range, phase change slope and MTIE during reference rearrangement) for
the following specifications.
1. AT&T TR62411 (DS1) December 1990 for Stratum 3, Stratum 4 Enhanced and Stratum 4
2. ANSI T1.101 (DS1) February 1994 for Stratum 3, Stratum 4 Enhanced and Stratum 4
3. ETSI 300 011 (E1) April 1992 for Single Access and Multi Access
4. TBR 4 November 1995
5. TBR 12 December 1993
6. TBR 13 January 1996
7. TU-T I.431 March 1993
Applications
This section contains MT9042C application specific details for clock and crystal operation, guard time usage, reset
operation, power supply decoupling, Manual Control operation and Automatic Control operation.
Master Clock
The MT9042C can use either a clock or crystal as the master timing source.
In Freerun Mode, the frequency tolerance at the clock outputs is identical to the frequency tolerance of the source
at the OSCi pin. For applications not requiring an accurate Freerun Mode, tolerance of the master timing source
may be ±100 ppm. For applications requiring an accurate Freerun Mode, such as AT&T TR62411, the tolerance of
the master timing source must Be no greater than ±32 ppm.
Another consideration in determining the accuracy of the master timing source is the desired capture range. The
sum of the accuracy of the master timing source and the capture range of the MT9042C will always equal
±230 ppm. For example, if the master timing source is ±100 ppm, then the capture range will be ±130 ppm.
Clock Oscillator - when selecting a Clock Oscillator, numerous parameters must be considered. This includes
absolute frequency, frequency change over temperature, output rise and fall times, output levels and duty cycle.
See AC Electrical Characteristics.
