REV. A
AD1838A
–17–
Table IV. Pin Function Changes in Auxiliary Mode
Pin Name I
2
S Mode Auxiliary Mode
ASDATA (O) I
2
S Data Out, Internal ADC TDM Data Out to SHARC.
DSDATA1 (I) I
2
S Data In, Internal DAC1 TDM Data In from SHARC.
DSDATA2 (I)/AAUXDATA1 (I) I
2
S Data In, Internal DAC2 AUX-I
2
S Data In 1 (from External ADC).
DSDATA3 (I)/AAUXDATA2 (I) I
2
S Data In, Internal DAC3 AUX-I
2
S Data In 2 (from External ADC).
AAUXDATA3 (I) Not Connected AUX-I
2
S Data In 3 (from External ADC).
ALRCLK (O) LRCLK for ADC TDM Frame Sync Out to SHARC (FSTDM).
ABCLK (O) BCLK for ADC TDM BCLK Out to SHARC.
DLRCLK (I)/AUXLRCLK (I/O) LRCLK In/Out Internal DACs AUX LRCLK In/Out. Driven by external LRCLK
from ADC in slave mode. In master mode,
driven by MCLK/512.
DBCLK (I)/AUXBCLK (I/O) BCLK In/Out Internal DACs AUX BCLK In/Out. Driven by external BCLK from
ADC in slave mode. In master mode, driven by
MCLK/8.
DAUXDATA (O) Not Connected AUX-I
2
S Data Out (to External DAC).
FSTDM
INTERNAL
ADC L1
AUX_ADC L2
AUX_ADC L3
AUX_ADC L4
INTERNAL
ADC R1
AUX_ADC R2
AUX_ADC R3
AUX_ADC R4
INTERNAL
DAC L1
INTERNAL
DAC L2
INTERNAL
DAC L3
INTERNAL
DAC R1
INTERNAL
DAC R2
INTERNAL
DAC R3
MSB TDM
1ST
CH
LEFT
RIGHT
I
2
S – MSB RIGHTI
2
S – MSB LEFT
BCLK
TDM
ASDATA1
TDM (OUT)
ASDATA
DSDATA1
TDM (IN)
DSDATA1
AUX
LRCLK I
2
S
(FROM AUX ADC NO. 1)
AUX
BCLK I
2
S
(FROM AUX ADC NO. 1)
AAUXDATA1 (IN)
(FROM AUX ADC NO. 1)
AAUXDATA2 (IN)
(FROM AUX ADC NO. 2)
AAUXDATA3 (IN)
(FROM AUX ADC NO. 3)
AUXBCLK FREQUENCY IS 64 FRAME RATE; TDM BCLK FREQUENCY IS 256 FRAME RATE.
TDM INTERFACEAUX – I
2
S INTERFACE
MSB TDM
8TH
CH
32
32
MSB TDM
1ST
CH
MSB TDM
8TH
CH
I
2
S – MSB RIGHTI
2
S – MSB LEFT
I
2
S – MSB RIGHTI
2
S – MSB LEFT
INTERNAL
DAC L4
INTERNAL
DAC R4
Figure 11. Auxiliary Mode Timing
