AD1838AASZ-REEL Datasheet AD1838AASZ, AD1838AASZ-REEL | P22-P24

REV. A

AD1838A

–21–

Table XII. ADC Control 3

Function

R/W IMCLK ADC DAC ADC

Address RES RES Reserved Clocking Scaling Peak Readback Test Mode Test Mode

15, 14, 13, 12 11 10 9, 8 7, 6 5 4, 3, 2 1, 0

1110 0 0 0, 0 00 = MCLK  20 = Disabled Peak Readback 000 = Normal Mode 00 = Normal Mode

01 = MCLK 1 = Enabled Peak Readback All Others Reserved All Others Reserved

10 = MCLK  2/3

11 = MCLK  2

Table IX. ADC Peak

Function

Four

Fixed

Address R/W RES Six Data Bits Bits

15, 14, 13, 12 11 10 9, 8, 7, 6, 5, 4 3, 2, 1, 0

1010 = Left ADC 1 0 000000 = 0 dBFS 0000

1011 = Right ADC 000001 = –1 dBFS

000010 = –2 dBFS These

four bits

are always

zero.

111111 = –63 dBFS

Table VIII. DAC Volume Control

Function

Address R/W RES DAC Volume

15, 14, 13, 12 11 10 9, 8, 7, 6, 5, 4, 3, 2, 1, 0

0010 = DACL1 0 0 0000000000 = Mute

0011 = DACR1 0000000001 = 1/1023

0100 = DACL2 0000000010 = 2/1023

0101 = DACR2 1111111110 = 1022/1023

0110 = DACL3 1111111111 = 1023/1023

0111 = DACR3

Table X. ADC Control 1

Function

ADC Sample

Address R/W RES Reserved Filter Power-Down Rate Reserved

15, 14, 13, 12 11 10 9 8 7 6 5, 4, 3, 2, 1, 0

1100 0 0 0 0 = All Pass 0 = Normal 0 = 48 kHz 0, 0, 0, 0, 0, 0

1 = High-Pass 1 = Power-Down 1 = 96 kHz 0, 0, 0, 0, 0, 0

Table XI. ADC Control 2

Function

Master/Slave ADC ADC Data- ADC MUTE

Address R/W RES Aux Mode Data Format Word Width AUXDATA RES Right Left

15, 14, 13, 12 11 10 9 8, 7, 6 5, 4 3 2 1 0

1101 0 0 0 = Slave 000 = I

S 00 = 24 Bits 0 = Off 0 0 = On 0 = On

1 = Master 001 = RJ 01 = 20 Bits 1 = On 1 = Mute 1 = Mute

010 = DSP 10 = 16 Bits

011 = LJ 11 = Reserved

100 = Packed 256

101 = Packed 128

110 = Auxiliary 256

111 = Auxiliary 512

101 = Packed 128

110 = Auxiliary 256

111 = Auxiliary 512

REV. A

AD1838A

–22–

CASCADE MODE

Dual AD1838A Cascade

The AD1838A can be cascaded to an additional AD1838A,

which, in addition to six external stereo ADCs and one external

stereo DAC, can be used to create a 32-channel audio system

with 16 inputs and 16 outputs. The cascade is designed to

connect to a SHARC DSP and operates in a time division

multiplexing (TDM) format. Figure 14 shows the connection

diagram for cascade operation. The digital interface for both

parts must be set to operate in Auxiliary 512 mode by program-

ming ADC Control Register 2. AD1838A No. 1 is set as a master

device by connecting the M/S pin to DGND and AD1838A

No. 2 is set as a slave device by connecting the M/S to ODVDD.

Both devices should be run from the same MCLK and PD/RST

signals to ensure that they are synchronized.

With Device 1 set as a master, it will generate the frame-sync

and bit clock signals. These signals are sent to the SHARC and

Device 2 ensuring that both know when to send and receive data.

The cascade can be thought of as two 256-bit shift registers, one

for each device. At the beginning of a sample interval, the shift

registers contain the ADC results from the previous sample

interval. The first shift register (Device 1) clocks data into the

SHARC and also clocks in data from the second shift register

(Device 2). While this is happening, the SHARC is sending

DAC data to the second shift register. By the end of the sample

interval, all 512 bits of ADC data in the shift registers will have

been clocked into the SHARC and been replaced by DAC data,

which is subsequently written to the DACs. Figure 15 shows the

timing diagram for the cascade operation.

AUX ADC

(SLAVE)

ALRCLK

ABCLK

ASDATA

DSDATA

ALRCLK

ABCLK

ASDATA

DSDATA

AD1838A NO. 1

(MASTER)

AD1838A NO. 2

(SLAVE)

SHARC

(SLAVE)

DOUT

LRCLK

BCLK

AUX ADC

(SLAVE)

DOUT

LRCLK

BCLK

AUX ADC

(SLAVE)

DOUT

LRCLK

BCLK

AUX ADC

(SLAVE)

DOUT

LRCLK

BCLK

AUX ADC

(SLAVE)

DOUT

LRCLK

BCLK

AUX ADC

(SLAVE)

DOUT

LRCLK

BCLK

AUXBCLK

AUXLRCLK

AUXDATA1

AUXDATA2

AUXDATA3

AUXBCLK

AUXLRCLK

AUXDATA1

AUXDATA2

AUXDATA3

DRx

RFSx

RCLKx

TCLKx

DTx

AUX DAC

(SLAVE)

DIN

LRCLK

BCLK

DAUXDATA

AUX DAC

(SLAVE)

DIN

LRCLK

BCLK

DAUXDATA

Figure 14. Dual AD1838A Cascade

AD1838A NO. 1 DACs

L1 L2 L3 R1 R2 R3

AD1838A NO. 2 DACs

L1 L2 L3 R1 R2 R3

RFSx

DTx

AD1838A NO. 1 ADCs

L1 L2 L3 L4 R1 R2 R3 R4

AD1838A NO. 2 ADCs

L1 L2 L3 L4 R1 R2 R3 R4

DRx

256 BCLKs

MSB MSB – 1

LSB

32 ABCLKs

BCLK

DTx

MSB

MSB – 1

LSB

DRx

DON’ T CARE

L4 R4 L4 R4

Figure 15. Dual AD1838A Cascade Timing

REV. A

AD1838A

–23–

5.76k

100pF

NPO

AUDIO

INPUT

600Z

47F

5.76k

120pF NPO

REF

5.76k 5.76k

REF

750k

237

1nF

NPO

237

1nF

NPO

100pF

NPO

ADCxP

ADCxN

OP275

Figure 16. Typical ADC Input Filter Circuit

3.01k

11k

270pF

NPO

560pF

NPO

68pF

NPO

11k

150pF

NPO

1.5k

5.62k

604

2.2nF

NPO

OUTNx

OUTPx

AUDIO

OUTPUT

OP275

Figure 17. Typical DAC Output Filter Circuit

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AD1838AASZ-REEL

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Interface - CODECs IC High perf Codec

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