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AD1838AASZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
REV. A
–3–
AD1838A
Parameter Min Typ Max Unit
ADC DECIMATION FILTER, 96 kHz*
Pass Band 43.54 kHz
Pass-Band Ripple ± 0.01 dB
Stop Band 52.46 kHz
Stop-Band Attenuation 120 dB
Group Delay 460 µs
DAC INTERPOLATION FILTER, 48 kHz*
Pass Band 21.77 kHz
Pass-Band Ripple ± 0.06 dB
Stop Band 28 kHz
Stop-Band Attenuation 55 dB
Group Delay 340 µs
DAC INTERPOLATION FILTER, 96 kHz*
Pass Band 43.54 kHz
Pass-Band Ripple ± 0.06 dB
Stop Band 52 kHz
Stop-Band Attenuation 55 dB
Group Delay 160 µs
DAC INTERPOLATION FILTER, 192 kHz*
Pass Band 81 kHz
Pass-Band Ripple ± 0.06 dB
Stop Band 97 kHz
Stop-Band Attenuation 80 dB
Group Delay 110 µs
DIGITAL I/O
Input Voltage High 2.4 V
Input Voltage Low 0.8 V
Output Voltage High ODVDD – 0.4 V
Output Voltage Low 0.4 V
Leakage Current ± 10 µA
POWER SUPPLIES
Supply Voltage (AVDD and DVDD) 4.5 5.0 5.5 V
Supply Voltage (ODVDD) 3.0 DVDD V
Supply Current I
ANALOG
84 95 mA
Supply Current I
ANALOG
,
Power-Down 55 67 mA
Supply Current I
DIGITAL
64 74 mA
Supply Current I
DIGITAL
,
Power-Down 1 4.5 mA
Dissipation
Operation, Both Supplies 740 mW
Operation, Analog Supply 420 mW
Operation, Digital Supply 320 mW
Power-Down, Both Supplies 280 mW
Power Supply Rejection Ratio
1 kHz, 300 mV p-p Signal at Analog Supply Pins –70 dB
20 kHz, 300 mV p-p Signal at Analog Supply Pins –75 dB
*Guaranteed by design.
Specifications subject to change without notice.
REV. A
AD1838A
–4–
TIMING SPECIFICATIONS
Parameter Min Max Unit Comments
MASTER CLOCK AND RESET
t
MH
MCLK High 15 ns
t
ML
MCLK Low 15 ns
t
PDR
PD/RST Low 20 ns
SPI PORT
t
CCH
CCLK High 40 ns
t
CCL
CCLK Low 40 ns
t
CCP
CCLK Period 80 ns
t
CDS
CDATA Setup 10 ns To CCLK Rising Edge
t
CDH
CDATA Hold 10 ns From CCLK Rising Edge
t
CLS
CLATCH Setup 10 ns To CCLK Rising Edge
t
CLH
CLATCH Hold 10 ns From CCLK Rising Edge
t
COE
COUT Enable 15 ns From CLATCH Falling Edge
t
COD
COUT Delay 20 ns From CCLK Falling Edge
t
COTS
COUT Three-State 25 ns From CLATCH Rising Edge
DAC SERIAL PORT (48 kHz and 96 kHz)
Normal Mode (Slave)
t
DBH
DBCLK High 60 ns
t
DBL
DBCLK Low 60 ns
f
DB
DBCLK Frequency 64 f
S
t
DLS
DLRCLK Setup 10 ns To DBCLK Rising Edge
t
DLH
DLRCLK Hold 10 ns From DBCLK Rising Edge
t
DDS
DSDATA Setup 10 ns To DBCLK Rising Edge
t
DDH
DSDATA Hold 10 ns From DBCLK Rising Edge
Packed 128/256 Modes (Slave)
t
DBH
DBCLK High 15 ns
t
DBL
DBCLK Low 15 ns
f
DB
DBCLK Frequency 256 f
S
t
DLS
DLRCLK Setup 10 ns To DBCLK Rising Edge
t
DLH
DLRCLK Hold 10 ns From DBCLK Rising Edge
t
DDS
DSDATA Setup 10 ns To DBCLK Rising Edge
t
DDH
DSDATA Hold 10 ns From DBCLK Rising Edge
ADC SERIAL PORT (48 kHz and 96 kHz)
Normal Mode (Master)
t
ABD
ABCLK Delay 25 ns From MCLK Rising Edge
t
ALD
ALRCLK Delay 5 ns From ABCLK Falling Edge
t
ABDD
ASDATA Delay 10 ns From ABCLK Falling Edge
Normal Mode (Slave)
t
ABH
ABCLK High 60 ns
t
ABL
ABCLK Low 60 ns
f
AB
ABCLK Frequency 64 f
S
t
ALS
ALRCLK Setup 5 ns To ABCLK Rising Edge
t
ALH
ALRCLK Hold 15 ns From ABCLK Rising Edge
t
ABDD
ASDATA Delay 15 ns From ABCLK Falling Edge
Packed 128/256 Mode (Master)
t
PABD
ABCLK Delay 40 ns From MCLK Rising Edge
t
PALD
LRCLK Delay 5 ns From ABCLK Falling Edge
t
PABDD
ASDATA Delay 10 ns From ABCLK Falling Edge
REV. A
–5–
AD1838A
Parameter Min Max Unit Comments
TDM256 MODE (Master, 48 kHz and 96 kHz)
t
TBD
BCLK Delay 40 ns From MCLK Rising Edge
t
FSD
FSTDM Delay 5 ns From BCLK Rising Edge
t
TABDD
ASDATA Delay 10 ns From BCLK Rising Edge
t
TDDS
DSDATA1 Setup 15 ns To BCLK Falling Edge
t
TDDH
DSDATA1 Hold 15 ns From BCLK Falling Edge
TDM256 MODE (Slave, 48 kHz and 96 kHz)
f
AB
BCLK Frequency 256 f
S
t
TBCH
BCLK High 17 ns
t
TBCL
BCLK Low 17 ns
t
TFS
FSTDM Setup 10 ns To BCLK Falling Edge
t
TFH
FSTDM Hold 10 ns From BCLK Falling Edge
t
TBDD
ASDATA Delay 15 ns From BCLK Rising Edge
t
TDDS
DSDATA1 Setup 15 ns To BCLK Falling Edge
t
TDDH
DSDATA1 Hold 15 ns From BCLK Falling Edge
TDM512 MODE (Master, 48 kHz)
t
TBD
BCLK Delay 40 ns From MCLK Rising Edge
t
FSD
FSTDM Delay 5 ns From BCLK Rising Edge
t
TABDD
ASDATA Delay 10 ns From BCLK Rising Edge
t
TDDS
DSDATA1 Setup 15 ns To BCLK Falling Edge
t
TDDH
DSDATA1 Hold 15 ns From BCLK Falling Edge
TDM512 MODE (Slave, 48 kHz )
f
AB
BCLK Frequency 512 f
S
t
TBCH
BCLK High 17 ns
t
TBCL
BCLK Low 17 ns
t
TFS
FSTDM Setup 10 ns To BCLK Falling Edge
t
TFH
FSTDM Hold 10 ns From BCLK Falling Edge
t
TBDD
ASDATA Delay 15 ns From BCLK Rising Edge
t
TDDS
DSDATA1 Setup 15 ns To BCLK Falling Edge
t
TDDH
DSDATA1 Hold 15 ns From BCLK Falling Edge
AUXILIARY INTERFACE (48 kHz and 96 kHz)
t
AXDS
AAUXDATA Setup 10 ns To AUXBCLK Rising Edge
t
AXDH
AAUXDATA Hold 10 ns From AUXBCLK Rising Edge
t
DXD
DAUXDATA Delay 20 ns From AUXBCLK Falling Edge
f
ABP
AUXBCLK Frequency 64 f
S
Slave Mode
t
AXBH
AUXBCLK High 15 ns
t
AXBL
AUXBCLK Low 15 ns
t
AXLS
AUXLRCLK Setup 10 ns To AUXBCLK Rising Edge
t
AXLH
AUXLRCLK Hold 10 ns From AUXBCLK Rising Edge
Master Mode
t
AUXBCLK
AUXBCLK Delay 20 ns From MCLK Rising Edge
t
AUXLRCLK
AUXLRCLK Delay 15 ns From AUXBCLK Falling Edge
Specifications subject to change without notice.
MCLK
t
MH
P
D/RST
t
ML
t
PDR
t
MCLK
Figure 1. MCLK and
PD
/
RST
Timing
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

AD1838AASZ

Mfr. #:
Buy AD1838AASZ
Manufacturer:
Analog Devices Inc.
Description:
Interface - CODECs IC High perf Codec
Lifecycle:
New from this manufacturer.
Delivery:
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