1 to 141 MHz EMI Reduction Oscillator
Page 5 of 9
Programmable Drive Strength
The SiT9005 includes a programmable drive strength feature
to provide a simple, flexible tool to optimize the clock rise/fall
time for specific applications. Benefits from the programmable
drive strength feature are:
Improves system radiated electromagnetic interference
(EMI) by slowing down the clock rise/fall time
Improves the downstream clock receiver’s (RX) jitter by
decreasing (speeding up) the clock rise/fall time.
Ability to drive large capacitive loads while maintaining full
swing with sharp edge rates.
For more detailed information about rise/fall time control and
drive strength selection, see the SiTime Application Notes
section: http://www.sitime.com/support/application-notes.
EMI Reduction by Slowing Rise/Fall Time
Figure 8 shows the harmonic power reduction as the rise/fall
times are increased (slowed down). The rise/fall times are
expressed as a ratio of the clock period. For the ratio of 0.05,
the signal is very close to a square wave. For the ratio of 0.45,
the rise/fall times are very close to near-triangular waveform.
These results, for example, show that the 11th clock harmonic
can be reduced by 35 dB if the rise/fall edge is increased from
5% of the period to 45% of the period.
Figure 8. Harmonic EMI reduction as a Function
of Slower Rise/Fall Time
Jitter Reduction with Faster Rise/Fall Time
Power supply noise can be a source of jitter for the
downstream chipset. One way to reduce this jitter is to
increase rise/fall time (edge rate) of the input clock. Some
chipsets would require faster rise/fall time in order to reduce
their sensitivity to this type of jitter. The SiT9005 provides up to
3 additional high drive strength settings for very fast rise/fall
time. Refer to the Vdd = 1.8V Rise/Fall Times
for Specific C
LOAD
to determine the proper drive strength.
High Output Load Capability
The rise/fall time of the input clock varies as a function of the
actual capacitive load the clock drives. At any given drive
strength, the rise/fall time becomes slower as the output load
increases. As an example, for a 3.3V SiT9005 device with
default drive strength setting, the typical rise/fall time is 1.1 ns
for 15 pF output load. The typical rise/fall time slows down to
2.9 ns when the output load increases to 45 pF. One can
choose to speed up the rise/fall time to 1.9 ns by then
increasing the drive strength setting on the SiT9005.
The SiT9005 can support up to 60 pF or higher in maximum
capacitive loads with up to 3 additional drive strength settings.
Refer to the Vdd = 1.8V Rise/Fall Times
for Specific C
LOAD
to determine the proper drive strength for the
desired combination of output load vs. rise/fall time
SiT9005 Drive Strength Selection
Tables Table 1 through Table 12 define the rise/fall time for a
given capacitive load and supply voltage.
Select the table that matches the SiT9005 nominal
supply voltage (1.8V, 2.5V, 2.8V, 3.3V).
Select the capacitive load column that matches the
application requirement (15 pF to 60 pF)
Under the capacitive load column, select the desired
rise/fall times.
The left-most column represents the part number code
for the corresponding drive strength.
Add the drive strength code to the part number for
ordering purposes.
Calculating Maximum Frequency
Based on the rise and fall time data given in Tables Table 1
through Table 12, the maximum frequency the oscillator can
operate with guaranteed full swing of the output voltage over
temperature as follows:
=
1
5 x Trf_20/80
Max Frequency
where Trf_20/80 is the typical rise/fall time at 20% to 80% Vdd
Example 1
Calculate f
MAX
for the following condition:
Vdd = 3.3V (Table 12)
Capacitive Load: 30 pF
Desired Tr/f time = 1.6ns (rise/fall time part number code = Z)
Part number for the above example:
Drive strength code is inserted here. Default setting is “-”
SiT9005AIZ14-33EB-105.12345
