10
Applications
Figures 9 and 10 show two possible circuit configurations,
AC coupled with a DC restore circuit and DC coupled with a
DC offset amplifier.
Due to the high clock rate, FCT (TTL/CMOS) or FAST (TTL)
glue logic should be used. FCT logic will tend to have large
overshoots if not loaded. Long traces (>2 or 3 inches) should
be terminated to maintain signal integrity.
FIGURE 9. TYPICAL AC COUPLED INPUT WITH DC RESTORE
FIGURE 10. TYPICAL DC COUPLED INPUT
12
13
14
15
23
24
1
2
V
RB
HI5714
V
RT
CLK
DGND
NC
NC
AGND
V
CCA
V
CCD
D7
D6
D5
D4
D3
D2
D1
D0
CLOCK
V
IN
NC
V
IN
OGND
V
CCO
V
CCO
+5VA
O/UF
OE
11
19
21
18
20
3
17
10
16
9
4
8
7
5
6
22
3.6V
1.3V
+5VA
+5VD
10
0.1
10
0.1
0.1
0.1
SAMPLE
PULSE
DC RESTORE
-
+
-
+
12
13
14
15
23
24
1
2
V
RB
HI5714
V
RT
CLK
DGND
NC
NC
AGND
V
CCA
V
CCD
D7
D6
D5
D4
D3
D2
D1
D0
CLOCK
V
IN
NC
V
IN
OGND
V
CCO
V
CCO
+5VA
O/UF
OE
11
19
21
18
20
3
17
10
16
9
4
8
7
5
6
22
3.6V
1.3V
+5VA
+5VD
10 0.1
10
0.1
0.1
0.1
+5VA
OFFSET
-
+
-
+
-
+
HI5714
11
Timing Definitions
Aperture Delay: Aperture delay is the time delay between
the external sample command (the rising edge of the clock)
and the time at which the signal is actually sampled. This
delay is due to internal clock path propagation delays.
Aperture Jitter: This is the RMS variation in the aperture
delay due to variation of internal clock path delays.
Data Latency
After the analog sample is taken, the data on the bus is
output at the next rising edge of the clock. This is due to the
output latch of the converter. This delay is specified as the
data latency. After the data latency time, the data
representing each succeeding sample is output at the
following clock pulse. The digital data lags the analog input
by 1 cycle.
Static Performance Definitions
Offset Error and Full-Scale Error use a measured value of
the external voltage reference to determine the ideal plus
and minus full-scale values. The results are all displayed in
LSBs.
Bottom Offset Voltage (V
OB
)
The first code transition should occur at a level 0.5 LSB
above the negative full-scale. Bottom offset voltage is
defined as the deviation of the actual code transition from
this point.
Top Offset Voltage (V
OT
)
The last code transition should occur for a analog input that
is 1.5 LSBs below positive full-scale. Top Offset Voltage is
defined as the deviation of the actual code transition from
this point.
Differential Linearity Error (DNL)
DNL is the worst case deviation of a code width from the
ideal value of 1 LSB. The converter is guaranteed to have no
missing codes.
Integral Linearity Error (INL)
INL is the worst case deviation of a code center from a best
fit straight line calculated from the measured data.
FIGURE 11. 8-BIT VIDEO COMPONENTS
A/D D/A
DSP/P
REFERENCE
ICL8069
AMP AMP
HA5020 (Single)
HA5022 (Dual)
HA5024 (Quad)
HA5013 (Triple)
HFA1105 (Single)
HFA1205 (Dual)
HFA1405 (Quad)
HI5714 (8-Bit) HSP9501
HSP48410
HSP48908
HSP48901
HSP48212
HSP43881
HSP43168
HI1171 (8-Bit)
CA3338 (8-Bit)
HI5721 (10-Bit)
HA5020 (Single)
HA2842 (Single)
HFA1115 (Single)
HFA1212 (Dual)
HFA1412 (Quad)
CMOS Logic Available in FCT
HSP9501: Programmable Data Buffer
HSP48410: Histogrammer/accumulating Buffer, 10-Bit Pixel Resolution, 4K x 4K Frame Size
HSP48908: 2-D Convolver, 3 x 3 Kernal Convolution, 8-Bit
HSP48901: 3 x 3 Image Filter, 30MHz, 8-Bit
HSP48212: Video Mixer
HSP43881: Digital Filter, 30MHz, 1-D and 2-D Fir Filters
HSP43168: Dual Fir Filter, 10-Bit, 33/45MHz
HI3050 (10-Bit)
HI5714
12
Dynamic Performance Definitions
Fast Fourier Transform (FFT) techniques are used to
evaluate the dynamic performance of the HI5714. A low
distortion sine wave is applied to the input, it is sampled, and
the output is stored in RAM. The data is then transformed
into the frequency domain with a 2048 point FFT and
analyzed to evaluate the dynamic performance of the A/D.
The sine wave input to the part is 0.5dB down from full scale
for these tests. The distortion numbers are quoted in dBc
(decibels with respect to carrier) and DO NOT include any
correction factors for normalizing to full scale.
Signal-to-Noise Ratio (SNR)
SNR is the measured RMS signal to RMS noise at a
specified input and sampling frequency. The noise is the
RMS sum of all of the spectral components except the
fundamental and the first five harmonics.
Signal-to-Noise + Distortion Ratio (SINAD)
SINAD is the measured RMS signal to RMS sum of all other
spectral components below the Nyquist frequency excluding
DC.
Effective Number Of Bits (ENOB)
The effective number of bits (ENOB) is derived from the
SINAD data. ENOB is calculated from:
ENOB = (SINAD - 1.76) / 6.02
2nd and 3rd Harmonic Distortion
This is the ratio of the RMS value of the 2nd and 3rd
harmonic component respectively to the RMS value of the
measured input signal.
Full Power Input Bandwidth
Full power bandwidth is the frequency at which the
amplitude of the digitally reconstructed output has
decreased 3dB below the amplitude of the input sine wave.
The input sine wave has a peak-to-peak amplitude equal to
the difference between the top reference voltage input and
the bottom reference voltage input. The bandwidth given is
measured at the specified sampling frequency.
HI5714

HI5714/4CB

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Lifecycle:
New from this manufacturer.
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