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NB4N11MDTG

P1-P3P4-P6P7-P9P10-P11
© Semiconductor Components Industries, LLC, 2005
November, 2005 − Rev. 1
1 Publication Order Number:
NB4N11M/D
NB4N11M
3.3 V 2.5 Gb/s Multi Level
Clock/Data Input to CML
Receiver/ Buffer/ Translator
Description
T h e N B4N11 M i s a d ifferential 1−to−2 clock/data
distribution/translation chip with CML output structure, targeted for
high−speed clock/data applications. The device is functionally
equivalent to the EP11, LVEP11, SG11 or 7L11M devices. Device
produces two identical differential output copies of clock or
data signal operating up to 2.5 GHz or 2.5 Gb/s, respectively. As such,
NB4N11M is ideal for SONET, GigE, Fiber Channel, Backplane and
other clock/data distribution applications.
Inputs accept LVPECL, CML, LVCMOS, LVTTL, or LVDS
(See Table 5). The CML outputs are 16 mA open collector
(See Figure 18) which requires resistor (R
L
) load path to V
TT
termination voltage. The open collector CML outputs must be
terminated to V
TT
at power up. Differential outputs produces
current–mode logic (CML) compatible levels when receiver loaded
with 50 W or 25 W loads connected to 1.8 V, 2.5 V or 3.3 V supplies
(see Figure 19). This simplifies device interface by eliminating a need
for coupling capacitors.
The device is offered in a small 8−pin TSSOP package.
Application notes, models, and support documentation are available
at www.onsemi.com.
Features
• Maximum Input Clock Frequency > 2.5 GHz
• Maximum Input Data Rate > 2.5 Gb/s
• Typically 1 ps of RMS Clock Jitter
• Typically 10 ps of Data Dependent Jitter @ 2.5 Gb/s, R
L
= 25 W
• 420 ps Typical Propagation Delay
• 150 ps Typical Rise and Fall Times
• Operating Range: V
CC
= 3.0 V to 3.6 V with V
EE
= 0 V and
V
TT
= 1.8 V to 3.6 V
• Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
EP, and SG Devices
• These are Pb−Free Devices*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
MARKING
DIAGRAM*
http://onsemi.com
TSSOP−8
DT SUFFIX
CASE 948R
1
8
E11M
ALYWG
G
1
8
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Figure 1. Functional Block Diagram
Q0
Q0
Q1
Q1
D
D
NB4N11M
http://onsemi.com
2
Figure 2. Pinout (Top View) and Logic Diagram
1
2
3
4
5
6
7
8
D
V
EE
V
CC
Q0
D
Q1
Q1
Q0
Table 1. Pin Description
Pin Name I/O Description
1 Q0 CML Output
Noninverted differential output. Typically receiver terminated with 50 W
resistor to V
TT
. Open collector CML outputs must be terminated to V
TT
at
powerup.
2 Q0 CML Output
Inverted differential output. Typically receiver terminated with 50 W resistor
to V
TT
. Open collector CML outputs must be terminated to V
TT
at powerup.
3 Q1 CML Output
Noninverted differential output. Typically receiver terminated with 50 W
resistor to V
TT
. Open collector CML outputs must be terminated to V
TT
at
powerup.
4 Q1 CML Output
Inverted differential output. Typically receiver terminated with 50 W resistor
to V
TT
. Open collector CML outputs must be terminated to V
TT
at powerup.
5 V
EE
− Negative supply voltage.
6 D LVPECL, CML, HSTL,
LVCMOS, LVDS, LVTTL Input
Inverted differential input.
7 D LVPECL, CML, HSTL,
LVCMOS, LVDS, LVTTL Input
Noninverted differential input.
8 V
CC
− Positive supply voltage.
NB4N11M
http://onsemi.com
3
Table 2. ATTRIBUTES
Characteristics Value
ESD Protection Human Body Model
Machine Model
> 1000 V
> 70 V
Moisture Sensitivity (Note 1) 8−TSSOP Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 197
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
Positive Power Supply V
EE
= −0.5 V 4 V
V
EE
Negative Power Supply V
CC
= +0.5 V −4 V
V
I
Positive Input
Negative Input
V
EE
= 0 V
V
CC
= 0 V
V
I
= V
CC
+0.4 V
V
I
= V
EE
–0.4 V
4
−4
V
V
V
O
Output Voltage Minimum
Maximum
V
EE
+ 600
V
CC
+ 400
mV
mV
T
A
Operating Temperature Range −40 to +85 °C
T
stg
Storage Temperature Range −65 to +150 °C
q
JA
Thermal Resistance (Junction−to−Ambient)
(Note 2)
0 lfpm
500 lfpm
TSSOP−8
TSSOP−8
190
130
°C/W
°C/W
q
JC
Thermal Resistance (Junction−to−Case) 1S2P (Note 2) TSSOP−8 41 to 44 °C/W
T
sol
Wave Solder < 3 Sec @ 260°C 265 °C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
2. JEDEC standard multilayer board − 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad.
P1-P3P4-P6P7-P9P10-P11

NB4N11MDTG

Mfr. #:
Buy NB4N11MDTG
Manufacturer:
ON Semiconductor
Description:
Clock Buffer MLTLVL IN-CML RECBUF
Lifecycle:
New from this manufacturer.
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