IRPLCFL5E
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In order to detect failure to strike conditions, the IR2520D performs an internal crest factor mea-
surement for detecting excessive dangerous currents or inductor saturation that can occur during a
lamp non-strike fault condition or a deactivated lamp condition. The IR2520D measures the VS pin
during the entire on-time of the low-side MOSFET. Should the peak current exceed the average
current by a factor of 5 during the on-time of LO, the IC will enter Fault Mode and both gate driver
outputs will be latched ‘low’.
Performing the crest factor measurement provides a relative current measurement that cancels
temperature and/or tolerance variations of the RDSon of the low-side half-bridge MOSFET and
does not need to be programmed differently for different lamp types. During normal operation, the
current will increase until the lamp ignites. After lamp ignition the current will decrease down to the
nominal current. Should a lamp non-strike condition occur where the filaments are intact but the
lamp does not ignite, the lamp voltage and output stage current will increase during the ignition
ramp until excessive currents occur or the resonant inductor saturates. The non-ZVS circuit or the
crest factor circuit will detect this condition and the IC will enter Fault Mode and both gate driver
outputs will be latched ‘low’. This will prevent damaging of the half-bridge MOSFETs.
Fig. 7.1 shows the inductor current and the lamp voltage in case of failure to strike condition to-
gether with the VCO pin voltage. At initial turn-on of the ballast, the frequency will ramp down from
fmax, through resonance, to fmin. If the lamp does not ignite, the inductor will saturate and high-
voltages will occur across the lamp as the frequency sweeps through resonance. The voltages and
currents in the output stage will decrease as the frequency continues to decrease to the capacitive
side of resonance. The voltages and currents will be low but hard-switching will occur (non-ZVS).
When the frequency reaches fmin (VCO > 4.6V), the non-ZVS and crest-factor protection will be
activated and the frequency will increase again to try and maintain ZVS. The frequency will sweep
back through resonance (from the capacitive side) and the crest-factor protection will shutdown the
IC on the first event when the inductor saturates to a level where the crest factor exceeds 5 (see
Fig. 7.1).
Fig. 7.2 shows pin LO, pin VS and the current in the resonant inductor during shutdown, with a
shorter time scale. The final shortened pulse of LO just before shutdown (Fig. 7.2) occurs due to the
internal 1us blank time of the crest-factor detection during each turn-on rising edge of LO (to pro-
vide immunity to noise and transients).
