XC9572XV High-performance CPLD
DS052 (v3.0) June 25, 2007 www.xilinx.com 5
Product Specification
R
Internal Timing Parameters
Figure 3: AC Load Circuit
Symbol Parameter
XC9572XV-5 XC9572XV-7
UnitsMin Max Min Max
Buffer Delays
T
IN
Input buffer delay - 2.0 - 2.3 ns
T
GCK
GCK buffer delay - 1.2 - 1.5 ns
T
GSR
GSR buffer delay - 2.0 - 3.1 ns
T
GTS
GTS buffer delay - 4.0 - 5.0 ns
T
OUT
Output buffer delay - 2.1 - 2.5 ns
T
EN
Output buffer enable/disable delay - 0 - 0 ns
Product Term Control Delays
T
PTCK
Product term clock delay - 1.7 - 2.4 ns
T
PTSR
Product term set/reset delay - 0.7 - 1.4 ns
T
PTTS
Product term 3-state delay - 5.0 - 7.2 ns
Internal Register and Combinatorial Delays
T
PDI
Combinatorial logic propagation delay - 0.2 - 1.3 ns
T
SUI
Register setup time 2.0 - 2.6 - ns
T
HI
Register hold time 1.5 - 2.2 - ns
T
ECSU
Register clock enable setup time 2.0 - 2.6 - ns
T
ECHO
Register clock enable hold time 1.5 - 2.2 - ns
T
COI
Register clock to output valid time - 0.2 - 0.5 ns
T
AOI
Register async. S/R to output delay - 5.9 - 6.4 ns
T
RAI
Register async. S/R recover before clock 5.0 7.5 ns
T
LOGI
Internal logic delay - 0.7 - 1.4 ns
T
LOGILP
Internal low power logic delay - 5.7 - 6.4 ns
Feedback Delays
T
F
Fast CONNECT II feedback delay - 1.6 - 3.5 ns
Time Adders
T
PTA
Incremental product term allocator delay - 0.7 - 0.8 ns
T
PTA2
Adjacent macrocell p-term allocator delay - 0.3 - 0.3 ns
T
SLEW
Slew-rate limited delay - 3.0 - 4.0 ns
R
1
V
TEST
C
L
R
2
Device Output
Output Type V
TEST
3.3V
2.5V
1.8V
R
1
320Ω
250Ω
10KΩ
R
2
360Ω
660Ω
14KΩ
C
L
35 pF
35 pF
35 pF
DS051_03_0601000
V
CCIO
3.3V
2.5V
1.8V
Product Obsolete/Under Obsolescence
