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AD7898AR-3REEL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
–3–REV. A
AD7898
Parameter Limit at T
MIN
, T
MAX
Unit Description
Mode 0 Operation
t
1
40 ns min CONVST Pulse Width
t
2
26
2
ns min SCLK High Pulse Width, V
DRIVE
= 5 V ± 5%
t
3
26
2
ns min SCLK Low Pulse Width, V
DRIVE
= 5 V ± 5%
30
2
ns min SCLK High Pulse Width V
DRIVE
= 2.7 V to 3.6 V
30
2
ns min SCLK Low Pulse Width V
DRIVE
= 2.7 V to 3.6 V
t
4
60
3
ns max Data Access Time after Falling Edge of SCLK, V
DRIVE
= 5 V ± 5%
t
4
70
3
ns max Data Access Time after Falling Edge of SCLK, V
DRIVE
= 2.7 V to 3.6 V
t
5
20 ns min Data Hold Time after Falling Edge of SCLK
t
6
50
4
ns max Bus Relinquish Time after Falling Edge of SCLK
t
CONVERT
3.3 µs
Mode 1 Operation
f
SCLK
5
1kHz min
3.7 MHz max
t
CONVERT
16 × t
SCLK
t
SCLK
= 1/f
SCLK
4.33 µs max f
SCLK
= 3.7 MHz
t
QUIET
100 ns min Minimum Quiet Time Required between Conversions
t
2
70 ns min CS to SCLK Setup Time
t
3
3
40 ns max Delay from CS Until SDATA Three-State Disabled
t
4
3
80 ns max Data Access Time after SCLK Falling Edge
t
5
108 ns min SCLK High Pulse Width
t
6
108 ns min SCLK Low Pulse Width
t
7
60 ns min SCLK to Data Valid Hold Time
t
8
4
20 ns min SCLK Falling Edge to SDATA High Impedance
60 ns max SCLK Falling Edge to SDATA High Impedance
t
POWER-UP
4.33 µs max Power-Up Time from Power-Down Mode
NOTES
1
Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
2
The SCLK maximum frequency is 15 MHz for Mode 0 operation for 220 kSPS throughput with V
DRIVE
= 5 V ± 5%, SCLK = 13 MHz with V
DRIVE
= 2.7 V to 3.6 V.
The mark/space ratio for SCLK is specified for at least 40% high time (with corresponding 60% low time) or 40% low time (with corresponding 60% high time). As
the SCLK frequency is reduced, the mark/space ratio may vary, provided limits are not exceeded. Care must be taken when interfacing to account for the data access
time, t
4
, and the set-up time required for the users processor. These two times will determine the maximum SCLK frequency that the user’s system can operate with.
See Serial Interface section.
3
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4
t
6
and t
8
are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapo-
lated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
6
and t
8
, quoted in the timing characteristics is the true bus
relinquish time of the part and is independent of the bus loading.
5
Mark/Space ratio for the SCLK input is 40/60 to 60/40.
Specifications subject to change without notice.
TIMING SPECIFICATIONS
1
(V
DD
= 4.75 V to 5.25 V; V
DRIVE
= 2.7 V to 5.25 V; REF IN = 2.5 V; T
A
= T
MIN
to T
MAX
, unless otherwise
noted.)
AD7898
–4– REV. A
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7898 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD pre-
cautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS*
(T
A
= 25°C unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Input Voltage to GND
AD7898-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 17 V
AD7898-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 V
Reference Input Voltage to GND . . . . –0.3 V to V
DD
+ 0.3 V
Digital Input Voltage to GND . . . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Output Voltage to GND . . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 170°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
ESD
AD7898-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 kV
AD7898-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 kV
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ORDERING GUIDE
Model Temperature Range Linearity Error
1
SNR Package Option
2
AD7898AR-10 –40°C to +85°C ± 1 LSB 71 dB R-8
AD7898AR-10REEL –40°C to +85°C ± 1 LSB 71 dB R-8
AD7898AR-10REEL7 –40°C to +85°C ± 1 LSB 71 dB R-8
AD7898ARZ-10
3
–40°C to +85°C ± 1 LSB 71 dB R-8
AD7898ARZ-10REEL
3
–40°C to +85°C ± 1 LSB 71 dB R-8
AD7898ARZ-10REEL7
3
–40°C to +85°C ± 1 LSB 71 dB R-8
AD7898AR-3 –40°C to +85°C ± 1 LSB 71 dB R-8
AD7898AR-3REEL –40°C to +85°C ± 1 LSB 71 dB R-8
AD7898AR-3REEL7 –40°C to +85°C ± 1 LSB 71 dB R-8
EVAL-AD7898CB
EVAL-CONTROL BRD2
4
NOTES
1
Linearity Error refers to integral linearity error.
2
R = SOIC.
3
Z = Pb-Free part.
4
This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
8
7
6
5
1
2
3
4
REF IN
V
IN
GND
SCLK
V
DD
CS / CONVST
V
DRIVE
SDATA
AD7898
200␮A
I
OH
200␮A
I
OL
TO
OUTPUT
PIN
C
L
50pF
1.6V
Figure 1. Load Circuit for Digital Output Timing
Specifications
–5–REV. A
AD7898
PIN FUNCTION DESCRIPTIONS
Pin Pin
No. Mnemonic Function
1 REF IN Voltage Reference Input. An external reference source should be connected to this pin to provide the
reference voltage for the AD7898’s conversion process. The REF IN input is buffered on-chip. The
nominal reference voltage for correct operation of the AD7898 is 2.5 V ± 5%. A 0.1 µF capacitor
should be placed on the REF IN pin.
2V
IN
Analog Input Channel. The analog input range is ± 10 V (AD7898-10) and ± 2.5 V (AD7898-3).
3 GND Analog Ground. Ground reference for track/hold, comparator, digital circuitry, and DAC.
4 SCLK Serial Clock Input. An external serial clock is applied to this input to obtain serial data from the AD7898.
When in Mode 0 operation, a new serial data bit is clocked out on the falling edge of this serial clock.
In Mode 0, data is guaranteed valid for 20 ns after this falling edge so that data can be accepted on the
falling edge when a fast serial clock is used. The serial clock input should be taken low at the end of
the serial data transmission. When in Mode 1 operation, SCLK also provides the serial clock for
accessing data from the part as in Mode 0, but this clock input is also used as the clock source for the
AD7898’s conversion process when in Mode 1.
5 SDATA Serial Data Output. Serial data from the AD7898 is provided at this output. The serial data is clocked
out by the falling edge of SCLK, but the data can also be read on the falling edge of SCLK. This is
possible because data bit N is valid for a specified time after the falling edge of SCLK (data hold time).
Sixteen bits of serial data are provided with four leading zeros followed by the 12 bits of conversion data,
which is provided MSB first. On the 16th falling edge of SCLK, the SDATA line is held for the data
hold time and then is disabled (three-stated). Output data coding is two’s complement for the AD7898.
6V
DRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the serial inter-
face of the AD7898 will operate.
7 CS/CONVST Chip Select/Convert Start. This pin is CONVST, an edge-triggered logic input when in Mode 0 operation.
On the falling edge of this input, the track/hold goes into its hold mode, and conversion is initiated.
When in Mode 1 operation, this pin is Chip Select, an active low logic input. This input provides the
dual function of initiating conversions on the AD7898 and also frames the serial data transfer.
8V
DD
Power Supply Input, 5 V ± 5%.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

AD7898AR-3REEL7

Mfr. #:
Buy AD7898AR-3REEL7
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 5V 12-Bit Serial 220 kSPS
Lifecycle:
New from this manufacturer.
Delivery:
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