AD7898
–6– REV. A
TERMINOLOGY
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (f
S
/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the quan-
tization noise. The theoretical signal to (noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
Thus for a 12-bit converter, this is 74 dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7898, it is defined as:
THD
VV VVV
V
() logdB =
++ ++
20
2
2
3
2
4
2
5
2
6
2
1
where V
1
is the rms amplitude of the fundamental, and V
2
, V
3
,
V
4
, V
5
, and V
6
are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f
S
/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n are equal to zero. For example, the second order
terms include (fa + fb) and (fa – fb), while the third order terms
include (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (fa – 2 fb).
The AD7898 is tested using the CCIF standard where two input
frequencies are used. In this case, the second and third order
terms are of different significance. The second order terms are
usually distanced in frequency from the original sine waves,
while the third order terms are usually at a frequency close to the
input frequencies. As a result, the second and third order terms
are specified separately. The calculation of the intermodulation
distortion is as per the THD specification where it is the ratio of
the rms sum of the individual distortion products to the rms
amplitude of the fundamental expressed in dBs.
Relative Accuracy
Relative accuracy or endpoint nonlinearity is the maximum
deviation from a straight line passing through the endpoints of
the ADC transfer function.
Differential Nonlinearity
This is the difference between the measured and the ideal
1LSB change between any two adjacent codes in the ADC.
Positive Full-Scale Error (AD7898-10)
This is the deviation of the last code transition (01 . . . 110 to
01 . . . 111) from the ideal (4 × VREF – 3/2 LSB) after the
Bipolar Zero Error has been adjusted out.
Positive Full-Scale Error (AD7898-3)
This is the deviation of the last code transition (01 . . . 110 to
01 . . . 111) from the ideal (VREF – 3/2 LSB) after the Bipolar
Zero Error has been adjusted out.
Bipolar Zero Error (AD7898-10, AD7898-3)
This is the deviation of the midscale transition (all 0s to all 1s)
from the ideal AGND – 1/2 LSB.
Negative Full-Scale Error (AD7898-10)
This is the deviation of the first code transition (10 . . . 000 to
10 . . . 001) from the ideal (–4 × VREF + 1/2 LSB) after Bipo-
lar Zero Error has been adjusted out.
Negative Full-Scale Error (AD7898-3)
This is the deviation of the first code transition (10 . . . 000 to
10 . . . 001) from the ideal (–VREF + 1/2 LSB) after Bipolar
Zero Error has been adjusted out.
Track/Hold Acquisition Time
Track/Hold acquisition time is the time required for the output
of the track/hold amplifier to reach its final value, within
± 1/2 LSB, after the end of conversion (the point at which the
track/hold returns to track mode). It also applies to situations
where there is a step input change on the input voltage applied
to the V
IN
input of the AD7898. This means that the user must
wait for the duration of the track/hold acquisition time after the
end of conversion, or after a step input change to V
IN
, before
starting another conversion to ensure that the part operates to
specification.
PSR (Power Supply Rejection)
Variations in power supply will affect the full-scale transition,
but not the converter’s linearity. Power Supply Rejection is the
maximum change in full-scale transition point due to change in
power-supply voltage from the nominal value.
PERFORMANCE CURVES
TPC 1 shows a typical FFT plot for the AD7898 at 220 kSPS
sampling rate with a 30 kHz input frequency while operating in
Mode 0.
SNR – dB
–15
–35
–55
–95
–115
5
–75
FREQUENCY – kHz
100806040200
8192 POINT FFT
f
SAMPLE
= 220kSPS
f
IN
= 30kHz
SINAD = 71.823dB
THD = –90.28dB
SFDR = –91.467dB
TPC 1. Mode 0 Dynamic Performance
TPC 2 shows a typical FFT plot for the AD7898 at 220 kSPS
sampling rate with a 30 kHz input frequency while operating in
Mode 1.
SNR – dB
–15
–35
–55
–95
–115
5
–75
FREQUENCY – kHz
100806040200
8192 POINT FFT
f
SAMPLE
= 220kSPS
f
IN
= 30kHz
SINAD = 71.779dB
THD = –88.337dB
SFDR = –89.639dB
TPC 2. Mode 1 Dynamic Performance
TPC 3 shows the Power Supply Rejection Ratio versus supply
frequency for the AD7898. The power supply rejection ratio is
defined as the ratio of the power in the ADC output at full-scale
frequency f, to the power of a 100 mV sine wave applied to the
ADC V
DD
supply of frequency f
S
.
PSRR (dB) = 10 log (Pf/Pfs)
Pf = Power at frequency f in ADC output, Pfs = power at fre-
quency fs coupled on to the ADC V
DD
supply input. Here a
100 mV peak-to-peak sine wave is coupled onto the V
DD
supply.
100 nF decoupling was used on the supply.
INPUT FREQUENCY – kHz
PSRR – dB
–40
–50
–70
–80
80604020100
–20
–30
–60
705030
TPC 3. PSRR vs. Supply Ripple Frequency
TPC 4 shows a graph of effective number of bits versus input
frequency while sampling at 220 kSPS.
INPUT FREQUENCY – kHz
EFFECTIVE NUMBER OF BITS
11.7
11.6
11.4
11.2
1008040200
11.9
11.8
11.5
60
11.3
TPC 4. Effective Number of Bits vs. Input Frequency at
220 kSPS
The effective number of bits for a device can be calculated from
its measured Signal to (Noise + Distortion) Ratio (see Termi-
nology section). TPC 4 shows a typical plot of effective number
of bits versus frequency for the AD7898 from dc to f
SAMPLE/2
.
The sampling frequency is 220 kSPS.
The formula for Signal to (Noise + Distortion) Ratio is related
to the resolution or number of bits in the converter. Rewriting
the formula, below, gives a measure of performance expressed in
effective number of bits (N):
N = (SNR – 1.76)/6.02
where SNR is Signal to (Noise + Distortion) Ratio.
–7–REV. A
Typical Performance Characteristics–AD7898
AD7898
–8– REV. A
INPUT FREQUENCY – kHz
SINAD – dB
–50
–55
–65
–75
100010010
–40
–45
–60
–70
V
DD
= V
DRIVE
= 5.25V
V
DD
= 5.0V, V
DRIVE
= 3.0V
V
DD
= V
DRIVE
= 4.75V
TPC 5. SINAD vs. Input Frequency at 220 kSPS
TPC 5 shows a graph of Signal to (Noise + Distortion)
ratio versus Input Frequency for various supply voltages
while sampling at 220 kSPS. The on-chip track-and-hold
can accommodate frequencies up to 4.7 MHz for AD7898-3,
and up to 3.6 MHz for AD7898-10, making the AD7898 ideal
for subsampling applications.
Noise
In an A/D converter, noise exhibits itself as a code uncertainty
in dc applications, and as the noise floor (in an FFT, for
example) in ac applications. In a sampling A/D converter like
the AD7898, all information about the analog input appears in
the baseband, from dc to half the sampling frequency. The input
bandwidth of the track/hold exceeds the Nyquist bandwidth
and, therefore, an antialiasing filter should be used to remove
unwanted signals above f
S
/2 in the input signal in applications
where such signals exist.
TPC 6 shows a histogram plot for 8192 conversions of a dc
input using the AD7898. The analog input was set at the center
of a code transition. It can be seen that almost all the codes
appear in one output bin, indicating very good noise perfor-
mance from the ADC.
5000
4000
2000
0
2050
6000
3000
1000
5500
4500
2500
500
3500
1500
204920482047204620452044
6500
TPC 6. Histogram of 8192 Conversions of a DC Input
CONVERTER DETAILS
The AD7898 is a fast, 12-bit single supply A/D converter. It
provides the user with signal scaling, track/hold, A/D converter,
and serial interface logic functions on a single chip. The A/D
converter section of the AD7898 consists of a conventional
successive-approximation converter based around an R-2R
ladder structure. The signal scaling on the AD7898-10 and
AD7898-3 allows the part to handle ±10 V and ± 2.5 V input
signals, respectively, while operating from a single 5 V supply.
The part requires an external 2.5 V reference. The reference
input to the part is buffered on-chip. The AD7898 has two
operating modes, an internal clocking mode using an on-chip
oscillator and an external clocking mode using the SCLK as
the master clock. The latter mode features a power-down
mechanism. These modes are discussed in more detail in the
Operating Modes section.
A major advantage of the AD7898 is that it provides all of the
above functions in an 8-lead SOIC package. This offers the user
considerable spacing saving advantages over alternative solutions.
The AD7898 consumes only 22.5 mW maximum, making it
ideal for battery-powered applications.
In Mode 0 operation, conversion is initiated on the AD7898 by
pulsing the CONVST input. On the falling edge of CONVST,
the on-chip track/hold goes from track to hold mode, and the
conversion sequence is started. The conversion clock for the
part is generated internally using a laser-trimmed clock oscilla-
tor circuit. Conversion time for the AD7898 is 3.3 µs, and the
quiet time is 0.1 µs. To obtain optimum performance from the
part in Mode 0, the read operation should not occur during the
conversion.
In Mode 1 operation, conversion is initiated on the AD7898 by
the falling edge of CS. Sixteen SCLK cycles are required to
complete the conversion and access the conversion result, after
which time CS may be brought high. The internal oscillator is
not used as the conversion clock in this mode as the SCLK is
used instead. The maximum SCLK frequency is 3.7 MHz in
Mode 1 providing a minimum conversion time of 4.33 µs. As in
Mode 0, another conversion should not be initiated during the
quiet time after the end of conversion.
Both of these modes of operation allow the part to operate
at throughput rates up to 220 kHz and achieve data sheet
specifications.
CIRCUIT DESCRIPTION
Analog Input Section
The AD7898 is offered as two part types: the AD7898-10,
which handles a ±10 V input voltage range; the AD7898-3,
which handles input voltage range ± 2.5 V.
V
IN
AGND
VREF
TO INTERNAL
COMPARATOR
TRACK/HOLD
TO ADC
REFERENCE
CIRCUITRY
R2
R3
R1
AD7898-10/AD7898-3
Figure 2. Analog Input Structure

AD7898AR-3REEL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 5V 12-Bit Serial 220 kSPS
Lifecycle:
New from this manufacturer.
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