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7132LA35C

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
10
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges
t
WC
ADDRESS
CE
R/W
DATA
IN
t
AS
(6)
t
EW
(2)
t
WR
(3)
t
DW
t
DH
t
AW
2692 drw 10
Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing)
(1,5,8)
Timing Waveform of Write Cycle No. 2, (CE Controlled Timing)
(1,5)
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W = VIL.
3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the
bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
t
WC
ADDRESS
OE
CE
R/W
DATA
OUT
DATA
IN
t
AS
(6)
t
OW
t
DW
t
DH
t
AW
t
WP
(2)
t
HZ
(7)
(4) (4)
t
WZ
(7)
t
HZ
(7)
2692 drw 09
t
WR
(3)
6.42
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges
11
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(7,8)
NOTES:
1. PLCC package only.
2. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port -to-Port Read and BUSY.”
3. To ensure that the earlier of the two ports wins.
4. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
5. To ensure that a write cycle is inhibited on port "B" during contention on port "A".
6. To ensure that a write cycle is completed on port "B" after contention on port "A".
7. 'X' in part numbers indicates power rating (SA or LA).
8. Industrial temperature: for specific speeds, packages and powers contact your sales office.
7132X20
(1)
7142X20
(1)
Com'l Only
7132X25
(2)
7142X25
(2)
Com'l, Ind
& Military
7132X35
7142X35
Com'l &
Military
Symbol Parameter Min.Max.Min.Max.Min.Max.Unit
BUSY Timing (For Master IDT7132 Only)
t
BAA
BUSY Access Time from Address
____
20
____
20
____
20 ns
t
BDA
BUSY Disable Time from Address
____
20
____
20
____
20 ns
t
BAC
BUSY Access Time from Chip Enable
____
20
____
20
____
20 ns
t
BDC
BUSY Disable Time from Chip Enable
____
20
____
20
____
20 ns
t
WDD
Write Pulse to Data Delay
(2)
____
50
____
50
____
60 ns
t
WH
Write Hold After BUSY
(6)
12
____
15
____
20
____
ns
t
DDD
Write Data Valid to Read Data Delay
(2)
____
35
____
35
____
35 ns
t
APS
Arbitration Priority Set-up Time
(3)
5
____
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(4)
____
25
____
35
____
35 ns
BUSY Timing (For Slave IDT7142 Only)
t
WB
Write to BUSY Input
(5)
0
____
0
____
0
____
ns
t
WH
Write Hold After BUSY
(6)
12
____
15
____
20
____
ns
t
WDD
Write Pulse to Data Delay
(2)
____
40
____
50
____
60 ns
t
DDD
Write Data Valid to Read Data Delay
(2)
____
30
____
35
____
35 ns
2692 tbl 11a
7132X55
7142X55
Com'l &
Military
7132X100
7142X100
Com'l &
Military
Symbol Parameter Min. Max. Min. Max. Unit
BUSY Timing (For Master IDT7132 Only)
t
BAA
BUSY Access Time from Address
____
30
____
50 ns
t
BDA
BUSY Disable Time from Address
____
30
____
50 ns
t
BAC
BUSY Access Time from Chip Enable
____
30
____
50 ns
t
BDC
BUSY Disable Time from Chip Enable
____
30
____
50 ns
t
WDD
Write Pulse to Data Delay
(2)
____
80
____
120 ns
t
WH
Write Hold After BUSY
(6 )
20
____
20
____
ns
t
DDD
Write Data Valid to Read Data Delay
(2)
____
55
____
100 ns
t
APS
Arbitration Priority Set-up Time
(3 )
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(4)
____
50
____
65 ns
BUSY Timing (For Slave IDT7142 Only)
t
WB
Write to BUSY Input
(5 )
0
____
0
____
ns
t
WH
Write Hold After BUSY
(6 )
20
____
20
____
ns
t
WDD
Write Pulse to Data Delay
(2)
____
80
____
120 ns
t
DDD
Write Data Valid to Read Data Delay
(2)
____
55
____
100 ns
2692 tbl 11b
12
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with BUSY
(4)
NOTES:
1. tWH must be met for both BUSY Input (IDT7142, slave) or Output (IDT7132, master).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB applies only to the slave version (IDT7142).
4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".
Timing Waveform of Write with Port-to-Port Read and BUSY
(2,3,4)
BUSY
"B"
2692 drw 12
R/W
"A"
t
WP
t
WH
(1)
t
WB
R/W
"B"
(2)
(3)
,
t
WC
t
WP
t
DW
t
DH
t
BDD
t
DDD
t
BDA
t
WDD
ADDR
"B"
DATA
OUT"B"
DATA
IN"A"
ADDR
"A"
MATCH
VALID
MATCH
VALID
R/W
"A"
BUSY
"B"
t
APS
(1)
2692 drw 11
t
BAA
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for Slave (IDT7142).
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

7132LA35C

Mfr. #:
Buy 7132LA35C
Manufacturer:
IDT
Description:
SRAM 16K(2KX8)CMOS DUALPORT RA
Lifecycle:
New from this manufacturer.
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