OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

7132LA35C

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
6.42
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges
7
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(3,5)
NOTES:
1. Transition is measured 0mV from Low or High-Impedance Voltage Output Test Load (Figure 2).
2. PLCC package only.
3. 'X' in part numbers indicates power rating (SA or LA).
4. This parameter is guaranteed by device characterization, but is not production tested.
5. Industrial temperature: for specific speeds, packages and powers contact your sales office.
7132X20
(2)
7142X20
(2)
Com'l Only
7132X25
(2)
7142X25
(2)
Com'l, Ind
& Military
7132X35
7142X35
Com'l &
Military
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.
READ CYCLE
t
RC
Read Cycle Time 20
____
25
____
35
____
ns
t
AA
Address Access Time
____
20
____
25
____
35 ns
t
ACE
Chip Enable Access Time
____
20
____
25
____
35 ns
t
AOE
Output Enable Access Time
____
11
____
12
____
20 ns
t
OH
Output Hold from Address Change 3
____
3
____
3
____
ns
t
LZ
Output Low-Z Time
(1,4)
0
____
0
____
0
____
ns
t
HZ
Output High-Z Time
(1,4)
____
10
____
10
____
15 ns
t
PU
Chip Enable to Power Up Time
(4)
0
____
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(4)
____
20
____
25
____
35 ns
2692 tbl 08a
7132X55
7142X55
Com'l &
Military
7132X100
7142X100
Com'l &
Military
UnitSymbol Parameter Min. Max. Min. Max.
READ CYCLE
t
RC
Read Cycle Time 55
____
100
____
ns
t
AA
Address Access Time
____
55
____
100 ns
t
ACE
Chip Enable Access Time
____
55
____
100 ns
t
AOE
Output Enable Access Time
____
25
____
40 ns
t
OH
Output Hold from Address Change 3
____
10
____
ns
t
LZ
Output Low-Z Time
(1,4)
5
____
5
____
ns
t
HZ
Output High-Z Time
(1,4)
____
25
____
40 ns
t
PU
Chip Enable to Power Up Time
(4)
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(4 )
____
50
____
50 ns
2692 tbl 08b
8
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 2, Either Side
(1)
NOTES:
1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW.
2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations, BUSY has
no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
4. Timing depends on which signal is asserted last, OE or CE.
5. Timing depends on which signal is de-asserted first, OE or CE.
Timing Waveform of Read Cycle No. 1, Either Side
(1)
ADDRESS
DATA
OUT
t
RC
t
OH
PREVIOUS DATA VALID
t
AA
t
OH
DATA VALID
2692 drw 07
t
BDDH
(2,3)
BUSY
OUT
CE
t
HZ
(5)
t
LZ
(4)
t
PD
(3)
VALID DATA
t
PU
50%
OE
DATA
OUT
CURRENT
I
CC
I
SS
50%
2692 drw 08
t
LZ
(4)
t
HZ
(5)
t
ACE
t
AOE
(3)
6.42
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges
9
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage Range
(5,6)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by device characterization
but is not production tested.
2. PLCC package only.
3. For Master/Slave combination, tWC = tBAA + tWP, since R/W = VIL must occur after tBAA.
4. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the
bus for the required tDW. If OE is High during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
5. 'X' in part numbers indicates power rating (SA or LA).
6. Industrial temperature: for specific speeds, packages and powers contact your sales office.
Symbol Parameter
7132X20
(2)
7142X20
(2)
Com'l Only
7132X25
(2)
7142X25
(2)
Com'l, Ind
& Military
7132X35
7142X35
Com'l &
Military
UnitMin. Max. Min. Max. Min. Max.
WRITE CYCLE
t
WC Write Cycle Time
(3)
20
____
25
____
35
____
ns
t
EW Chip Enable to End-of-Write 15
____
20
____
30
____
ns
t
AW Address Valid to End-of-Write 15
____
20
____
30
____
ns
t
AS Address Set-up Time 0
____
0
____
0
____
ns
t
WP Write Pulse Width
(4)
15
____
15
____
25
____
ns
t
WR Write Recovery Time 0
____
0
____
0
____
ns
t
DW Data Valid to End-of-Write 10
____
12
____
15
____
ns
t
HZ Output High-Z Time
(1)
____
10
____
10
____
15 ns
t
DH Data Hold Time 0
____
0
____
0
____
ns
t
WZ Write Enable to Output in High-Z
(1)
____
10
____
10
____
15 ns
t
OW Output Active from End-of-Write
(1)
0
____
0
____
0
____
ns
2692 tbl 09
Symbol Parameter
7132X55
7142X55
Com'l &
Military
7132X100
7142X100
Com'l &
Military
UnitMin. Max. Min. Max.
WRITE CYCLE
t
WC
Write Cycle Time
(3)
55
____
100
____
ns
t
EW
Chip Enable to End-of-Write 40
____
90
____
ns
t
AW
Address Valid to End-of-Write 40
____
90
____
ns
t
AS
Address Set-up Time 0
____
0
____
ns
t
WP
Write Pulse Width
(4)
30
____
55
____
ns
t
WR
Write Recovery Time 0
____
0
____
ns
t
DW
Data Valid to End-of-Write 20
____
40
____
ns
t
HZ
Output High-Z Time
(1)
____
25
____
40 ns
t
DH
Data Hold Time 0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1 )
____
30
____
40 ns
t
OW
Output Active from End-of-Write
(1)
0
____
0
____
ns
2692 tbl 10
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

7132LA35C

Mfr. #:
Buy 7132LA35C
Manufacturer:
IDT
Description:
SRAM 16K(2KX8)CMOS DUALPORT RA
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet