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MAX1138EEE+T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
MAX1136–MAX1139
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial 10-Bit ADCs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 2.7V to 3.6V (MAX1137/MAX1139), V
DD
= 4.5V to 5.5V (MAX1136/MAX1138), V
REF
= 2.048V (MAX1137/MAX1139), V
REF
=
4.096V (MAX1136/MAX1138), f
SCL
= 1.7MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C. See
Tables 1–5 for programming notation.)
TIMING CHARACTERISTICS (Figure 1)
(V
DD
= 2.7V to 3.6V (MAX1137/MAX1139), V
DD
= 4.5V to 5.5V (MAX1136/MAX1138), V
REF
= 2.048V (MAX1137/MAX1139), V
REF
=
4.096V (MAX1136/MAX1138), f
SCL
= 1.7MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C. See
Tables 1–5 for programming notation.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER REQUIREMENTS
Power-Supply Rejection Ratio PSRR Full-scale input (Note 9) ±0.01 ±0.5 LSB/V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING CHARACTERISTICS FOR FAST MODE
Serial Clock Frequency f
SCL
400 kHz
Bus Free Time Between a
STOP (P) and a
START (S) Condition
t
BUF
1.3 µs
Hold Time for START (S) Condition t
HD
,
STA
0.6 µs
Low Period of the SCL Clock t
LOW
1.3 µs
High Period of the SCL Clock t
HIGH
0.6 µs
Setup Time for a Repeated START
Condition (Sr)
t
SU
,
STA
0.6 µs
Data Hold Time t
HD
,
DAT
(Note 10) 0 900 ns
Data Setup Time t
SU
,
DAT
100 ns
Rise Time of Both SDA and SCL
Signals, Receiving
t
R
Measured from 0.3V
DD
to 0.7V
DD
20 + 0.1C
B
300 ns
Fall Time of SDA Transmitting
t
F
Measured from 0.3V
DD
to 0.7V
DD
(Note 11) 20 + 0.1C
B
300 ns
Setup Time for STOP (P) Condition t
SU
,
STO
0.6 µs
Capacitive Load for Each Bus Line C
B
400 pF
Pulse Width of Spike Suppressed t
SP
50 ns
TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (C
B
= 400pF, Note 12)
Serial Clock Frequency f
SCLH
(Note 13) 1.7 MHz
Hold Time, Repeated START
Condition (Sr)
t
HD
,
STA
160 ns
Low Period of the SCL Clock t
LOW
320 ns
High Period of the SCL Clock t
HIGH
120 ns
Setup Time for a Repeated START
Condition (Sr)
t
SU
,
STA
160 ns
Data Hold Time t
HD
,
DAT
(Note 10) 0 150 ns
Data Setup Time t
SU
,
DAT
10 ns
Note 1: For DC accuracy, the MAX1136/MAX1138 are tested at V
DD
= 5V and the MAX1137/MAX1139 are tested at V
DD
= 3V. All
devices are configured for unipolar, single-ended inputs.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Note 3: Offset nulled.
Note 4: Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion
time does not include acquisition time. SCL is the conversion clock in the external clock mode.
Note 5: A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
Note 6: The absolute input-voltage range for the analog inputs (AIN0–AIN11) is from GND to V
DD
.
Note 7: When the internal reference is configured to be available at AIN_/REF (SEL[2:1] = 11) decouple AIN_/REF to GND with a
0.1µF capacitor and a 2kΩ series resistor (see the
Typical Operating Circuit
).
Note 8: ADC performance is limited by the converter’s noise floor, typically 300µV
P-P
.
Note 9: Measured as for the MAX1137/MAX1139
and for the MAX1136/MAX1138
Note 10: A master device must provide a data hold time for SDA (referred to V
IL
of SCL) in order to bridge the undefined region of
SCL’s falling edge (see Figure 1).
Note 11: The minimum value is specified at +25°C.
Note 12: C
B
= total capacitance of one bus line in pF.
Note 13: f
SCL
must meet the minimum clock low time plus the rise/fall times.
VVVV
V
VV
FS FS
REF
N
(. ) (. )
(. . )
55 45
21
55 45
−
−
−
[]
×
⎡
⎣
⎢
⎤
⎦
⎥
VVVV
V
VV
FS FS
REF
N
(. ) (. )
(. . )
36 27
21
36 27
−
−
−
[]
×
⎡
⎣
⎢
⎤
⎦
⎥
MAX1136–MAX1139
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial 10-Bit ADCs
_______________________________________________________________________________________ 5
TIMING CHARACTERISTICS (Figure 1) (continued)
(V
DD
= 2.7V to 3.6V (MAX1137/MAX1139), V
DD
= 4.5V to 5.5V (MAX1136/MAX1138), V
REF
= 2.048V (MAX1137/MAX1139), V
REF
=
4.096V (MAX1136/MAX1138), f
SCL
= 1.7MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C. See
Tables 1–5 for programming notation.).)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Rise Time of SCL Signal
(Current Source Enabled)
t
RCL
Measured from 0.3V
DD
to 0.7V
DD
20 80 ns
Rise Time of SCL Signal after
Acknowledge Bit
t
RCL1
Measured from 0.3V
DD
to 0.7V
DD
20 160 ns
Fall Time of SCL Signal t
FCL
Measured from 0.3V
DD
to 0.7V
DD
20 80 ns
Rise Time of SDA Signal t
RDA
Measured from 0.3V
DD
to 0.7V
DD
20 160 ns
Fall Time of SDA Signal t
FDA
Measured from 0.3V
DD
to 0.7V
DD
(Note 11) 20 160 ns
Setup Time for STOP (P) Condition t
SU
,
STO
160 ns
Capacitive Load for Each Bus Line C
B
400 pF
Pulse Width of Spike Suppressed t
SP
(Notes 10 and 13) 0 10 ns
MAX1136–MAX1139
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial 10-Bit ADCs
6 _______________________________________________________________________________________
Typical Operating Characteristics
(V
DD
= 3.3V (MAX1137/MAX1139), V
DD
= 5V (MAX1136/MAX1138), f
SCL
= 1.7MHz, external clock, f
SAMPLE
= 94.4ksps, single-
ended, unipolar, T
A
= +25°C, unless otherwise noted.)
-0.3
-0.1
-0.2
0.1
0
0.2
0.3
0 1000
DIFFERENTIAL NONLINEARITY
vs. DIGITAL CODE
MAX1136 toc01
DIGITAL OUTPUT CODE
DNL (LSB)
400200 600 800
-0.5
-0.2
-0.3
-0.4
-0.1
0
0.1
0.2
0.3
0.4
0.5
0 400200 600 800 1000
INTEGRAL NONLINEARITY
vs. DIGITAL CODE
MAX1136 toc02
DIGITAL OUTPUT CODE
INL (LSB)
-160
-140
-120
-100
-80
-60
-40
-20
0
0 10k 20k 30k 40k 50k
FFT PLOT
MAX1136 toc03
FREQUENCY (Hz)
AMPLITUDE (dBc)
f
SAMPLE
= 94.4ksps
f
IN
= 10kHz
300
400
350
500
450
600
550
650
750
700
800
-40 -10 5-25 20 35 50 65 80
SUPPLY CURRENT vs. TEMPERATURE
MAX1136 toc04
TEMPERATURE (
°
C)
SUPPLY CURRENT (µA)
INTERNAL REFERENCE
MAX1138/1136
MAX1139/1137
MAX1138/1136
MAX1139/1137
INTERNAL REFERENCE
EXTERNAL REFERENCE
EXTERNAL REFERENCE
SETUP BYTE
EXT REF: 10111011
INT REF: 11011011
0
0.10
0.05
0.20
0.15
0.30
0.25
0.35
0.45
0.40
0.50
-40 -10 5
-25
20 35 50 65 80
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX1136 toc06
TEMPERATURE (
°
C)
SUPPLY CURRENT (µA)
MAX1138
MAX1139
200
300
250
350
400
450
500
550
600
650
700
750
800
0 20 30 40 60 80 100
AVERAGE SUPPLY CURRENT vs.
CONVERSION RATE (EXTERNAL CLOCK)
MAX1136 toc07
CONVERSION RATE (ksps)
AVERAGE I
DD
(µA)
010 50 70 90
A
B
A) INTERNAL REFERENCE ALWAYS ON
B) EXTERNAL REFERENCE
MAX1138
0.9990
0.9994
0.9992
0.9998
0.9996
1.0002
1.0000
1.0004
1.0008
1.0006
1.0010
-40 -10 5-25 20 35 50 65 80
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1136 toc08
TEMPERATURE (°C)
V
REF
NORMALIZED
MAX1138
MAX1139
NORMALIZED TO REFERENCE VALUE
AT +25
°
C
0.99990
0.99994
0.99992
0.99998
0.99996
1.00002
1.00000
1.00004
1.00008
1.00006
1.00010
2.7 3.3 3.6 3.93.0 4.2 4.5 4.8 5.1 5.4
NORMALIZED REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
MAX1136 toc09
V
DD
(V)
V
REF
NORMALIZED
MAX1138/MAX1136,
NORMALIZED TO
REFERENCE VALUE AT
V
DD
= 5V
MAX1139/MAX1137,
NORMALIZED TO
REFERENCE VALUE AT
V
DD
= 3.3V
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

MAX1138EEE+T

Mfr. #:
Buy MAX1138EEE+T
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 10-Bit 12Ch 94.4ksps 5.5V Precision ADC
Lifecycle:
New from this manufacturer.
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