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0
100
200
300
400
500
600
10 20 30 40 50 60 70 80 90
R
OSC
(kW)
Figure 25. Frequency vs. R
OSC
F
SW
(kHz)
Table 1. Frequency vs. R
OSC
F
SW
(kHz)
R
OSC
(kW)
170 51.1
250 34.8
300 28.7
360 23.2
500 16.2
The softstart time can be estimated as follows:
T
SS
[
F
0
F
SW
@ T
SS0
Where: T
SS
: softstart time [s]
F
0
: specified frequency [Hz]
T
SS0
: softstart time at specified frequency [s]
(3) Current Sensor Selection
Current sensing for average current mode control relies on
the inductor current signal. This is translated into a voltage
via a current sensor, which is then measured differentially by
the current sense amplifier, generating a singleended
output to use as a control signal. The easiest means of
implementing this transresistance is through the use of a
sense resistor in series with the output inductor and
capacitors. A sense resistor should be selected as follows:
R
S
+
V
CL
I
CL
Where: R
S
: sense resistor [W]
V
CL
: current limit threshold voltage [V]
I
CL
: desired current limit [A]
Alternative methods, such as lossless inductor current
sensing, are feasible but beyond the scope of this document.
(4) Output Inductor Selection
Both mechanical and electrical considerations influence
the selection of an output inductor. From a mechanical
perspective, smaller inductor values generally correspond to
smaller physical size. Since the inductor is often one of the
largest components in the power supply, a minimum
inductor value is particularly important in space
constrained applications. From an electrical perspective, an
inductor is chosen for a set amount of current ripple and to
assure adequate transient response.
Larger inductor values limit the switchers ability to slew
current through the output inductor in response to output load
transients, impacting the dynamic response. While the
inductor is slewing current during this time, output capacitors
must supply the load current. Therefore, decreasing the
inductance allows for less output capacitance to hold the
output voltage up during a load step. Load transient
simulation is a powerful tool in anticipating this response.
For switchers with both cyclebycycle overcurrent
protection (OCP) and average current limiting (ACL), the
OCP and ACL references are compared to the sensed current
via sense resistance, R
S
. A minimum inductance is required
to prevent the OCP from tripping during the onset of ACL
during typical operation as follows:
L
MIN
+
V
OUT
(1 * D)
2 @ F
SW
@
R
S
DV
CL
Where: L
MIN
: minimum inductance to assure OCP and ACL
do not both trip [H]
DV
CL
: difference between OCP and ACL threshold
voltages [V]
For switchers that use the current signal of the inductor for
control purposes, the voltage ripple over the sense resistance
must be sufficient in magnitude to counteract the
contribution due to inherent comparator offsets and other
errors, as follows:
L
MAX
+
V
OUT
@ (1 * D
MAX
)
F
SW
@
R
S
Ë
L
@ V
CL
Where: L
MAX
: maximum inductance to assure adequate
voltage ripple over the sense resistance [H]
κ
L
: inductor peaktopeak current ripple to current
limit ratio [%]
V
CL
: threshold voltage for the current limit [V]
As a rule of thumb, ensuring that κ
L
is at least 5% to 10%
has been empirically sufficient.
Smaller values of inductance increase the regulators
maximum achievable slew rate and decrease the necessary
capacitance, at the expense of higher ripple current, which
causes higher output voltage ripple. The peaktopeak
ripple current is given by the following equation:
i
L
+
V
OUT
@ (1 * D)
L @ F
SW
Where: i
L
: peaktopeak output current ripple [App]
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The ripple current is at a maximum when the duty cycle
is at a minimum value and vice versa, as follows:
i
L(max)
+
V
OUT
@ (1 * D
MIN
)
L @ F
SW
i
L(min)
+
V
OUT
@ (1 * D
MAX
)
L @ F
SW
Where: i
L(max)
: maximum inductor current ripple [App]
i
L(min)
: minimum inductor current ripple [App]
From this equation it is clear that the ripple current
increases as L decreases, emphasizing the tradeoff between
dynamic response and ripple current. The peak and valley
values of the triangular current waveform are as follows:
I
L(pk)
+ I
OUT
)
i
L
2
I
L(vly)
+ I
OUT
*
i
L
2
Where: I
L(pk)
: peak (maximum) value of ripple current [A]
I
L(vly)
: valley (minimum) value of ripple current [A]
Saturation current is specified by inductor manufacturers
as the current at which the inductance value has dropped a
certain percentage from the nominal value, typically 10%.
For stable operation, the output inductor must be chosen so
that the inductance is close to the nominal value even at the
peak output current, I
L(pk)
. It is recommended to choose an
inductor with saturation current sufficiently higher than the
peak output current, such that the inductance is very close to
the nominal value at the peak output current. This introduces
a safety factor and allows for more optimized compensation.
Inductor efficiency is another consideration when
selecting an output inductor. Inductor losses include dc and
ac winding losses and core losses. Core losses include eddy
current losses, which are very low due to high core
resistance, and magnetic hysteresis losses, which increase
with peaktopeak ripple current. Core losses also increase
as switching frequency increases.
Ac winding losses are based on the ac resistance of the
winding and the RMS ripple current through the inductor,
which is much lower than the dc current. The ac winding
losses are due to skin and proximity effects and are typically
much less than the dc losses, but increase with frequency. Dc
winding losses account for a large percentage of output
inductor losses and are the dominant factor at switching
frequencies at or below 500 kHz. The dc winding losses in
the inductor can be calculated with the following equation:
P
L(dc)
+ I
OUT
2
@ R
dc
Where: P
L(dc)
: dc winding losses in the output inductor
R
dc
: dc resistance of the output inductor (DCR)
As can be seen from the above equation, to minimize
inductor losses, an inductor with very low DCR should be
chosen.
(5) Output Capacitor Selection
The output capacitor is a basic component for the fast
response of the power supply. During a load step, for the first
few microseconds, it supplies the current to the load. The
controller immediately recognizes the load step and
increases the duty cycle, but the current slope is limited by
the inductors slew rate. During a load release, the output
voltage will overshoot. The capacitance will dampen this
undesirable response, decreasing the amount of voltage
overshoot.
In the case of stepping into a short, the inductor current
approaches zero with the worst case initial current at the
current limit and the initial voltage at the output voltage set
point, calculating the voltage overshoot as follows:
DV
OS
+
L @ I
CL
2
C
) V
OUT
2
* V
OUT
Ǹ
Accordingly, a minimum amount of capacitance can be
chosen for a maximum allowed output voltage overshoot:
C
MIN
+
L @ I
CL
2
(V
OUT
) DV
OS(max)
)
2
* V
OUT
2
Where: C
MIN
: minimum amount of capacitance to minimize
voltage overshoot to DV
OS(max)
[F]
DV
OS(max)
: maximum allowed voltage overshoot
during a short [V]
A maximum amount of capacitance can be found based on
the inrush current and current limit. To calculate the input
startup current, the following equation can be used:
I
INRUSH
+
C
OUT
@ V
OUT
t
SS
) I
OUT(i)
Where: I
INRUSH
: input current during startup
I
OUT(i)
: initial output current
If the inrush current is higher than the steadystate input
current with the maximum load, then the input fuse should
be rated accordingly, if one is used. During softstart, the
inductor current must provide current to the load, as well as
current to charge the output capacitor. The maximum current
which the inductor is allowed to conduct is the current limit.
Setting the inrush current to the current limit, this puts a limit
on the maximum capacitor size, as follows:
C
MAX
+
(I
CL
* I
OUT(i)
) @ t
SS
V
OUT
Where: C
MAX
: maximum output capacitance [F]
Capacitors should also be chosen to provide acceptable
output voltage ripple with a dc load, in addition to limiting
voltage overshoot during a dynamic response. Key
specifications are equivalent series resistance (ESR) and
equivalent series inductance (ESL). The output capacitors
must have very low ESL for best transient response. The
PCB traces will add to the ESL, but by putting the output
capacitors close to the load, this effect can be minimized and
ESL neglected in determining output voltage ripple.
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The capacitance itself causes a voltage ripple due to the
current ripple. This is as follows:
V
Q
+ i
L
@
D
C @ F
SW
Where: v
Q
: output voltage ripple due to output capacitance
[Vpp]
Also, the ripple current through the inductor causes a
voltage ripple over the output capacitor due to its ESR as
follows:
V
ESR
+ i
L
@ R
ESR
Where: v
ESR
: output voltage ripple due to the effects of ESR
[Vpp]
R
ESR
: total ESR of output capacitors [W]
Typically, the ripple due to ESR dominates, having the
largest effect on output voltage ripple. The total output
voltage ripple in steadystate operation can be calculated as
follows:
V
OUT
+ V
Q
) V
ESR
+ Ë
C
@ V
OUT
Where: v
OUT
: total output voltage ripple [Vpp]
κ
C
: percent output voltage ripple [%]
Typically, the voltage ripple percentage is a performance
parameter used to decide on the desired output capacitor.
The maximum total effective ESR of the output capacitors
is calculated as follows:
R
ESR(max)
+
V
OUT
* V
Q
i
L(max)
Where: R
ESR(max)
: maximum allowable total ESR of output
capacitors
It should be noted that these values of ESR are at the
switching frequency and ESR decreases as frequency
increases. The steadystate power lost due to the ESR of the
output capacitor can be calculated as follows:
P
C(ESR)
+
1
3
i
L
2
@ R
ESR
(6) Input Capacitor Selection
The input capacitors have to sustain the ripple current
produced during the on time of the highside MOSFET and
must have a low ESR to minimize the losses. The RMS value
of this ripple is:
I
IN(RMS)
+ I
OUT
D @ (1 * D)
Ǹ
Where: I
IN(RMS)
= input RMS current
The large majority of the ripple spectrum will be at the
switching frequency. The above equation reaches its
maximum value with D = 0.5, I
IN(RMS)
= I
OUT
/2. The input
capacitors must be rated to handle a ripple current of
onehalf the maximum output current at the switching
frequency.
ESR is the majority cause of losses in the input capacitors.
Losses in the input capacitors can be calculated with the
following equation:
P
CIN
+ I
IN(RMS)
2
@ R
ESR(CIN)
Where: P
CIN
= power loss in the input capacitors
R
ESR(CIN)
= effective series resistance of the input
capacitance
Due to large current transients through the input
capacitors, electrolytic, polymer or ceramics should be used.
If a tantalum must be used, it must be surge protected, to
prevent against capacitor failure. Due to the large ripple
current, it is common to put small ceramic capacitors in
parallel with the bulk input capacitors, which will handle a
significant portion of the ripple current. A value of 0.01 mF
to 0.1 mF placed near the MOSFETs is recommended.
(7) Compensator Design
The purpose of the compensators is to stabilize the
dynamic response of the converter. By optimizing the
compensators, stable regulation with fast input line and
output load transient response is achieved.
Compensator design is related to the placement of zeros
and poles in the closed loop, in order to assure stability with
optimized transient response. The general approach is to use
some rule of thumb values and then tune them through
simulation to optimize load step response, while assuring
stability over line and load variations.
TypeII compensators are used with the two error
amplifiers in average current mode control. The CEA closes
the inner currentloop and the VEA closes the outer
voltageloop. As a rule of thumb, a zero is placed in each
loop with the intent to compensate the effects of the double
pole from the output inductor and capacitor. Additionally, a
pole is placed at origin, due to the negative feedback, and a
pole is also placed in each loop with the intent to compensate
the effects of the double righthalfplane zero from the
current sampling function.
The crossover frequency is then set so that gain limitations
of the error amplifier are not exceeded. The compensator
must assure there is adequate phase margin in the total
closedloop response, which can be analyzed on a
smallsignal basis. Further reduction in loop gain, via
decreasing the crossover frequency, may be required to
avoid largesignal clamping limitations; this effect can be
seen in simulation and taken care of in the compensator
tuning process.

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LDO Voltage Controllers AUTOMTVE GRD SYNCHRN
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