MC74HCT366ADTG

© Semiconductor Components Industries, LLC, 2014
March, 2014 Rev. 2
1 Publication Order Number:
MC74HCT366A/D
MC74HCT366A
Hex 3-State Inverting
Buffer with Common
Enables and LSTTL
Compatible Inputs
HighPerformance SiliconGate CMOS
The MC74HCT366A is identical in pinout to the LS366. The device
inputs are compatible with standard CMOS or LSTTL outputs.
This device is a highspeed hex buffer with 3state outputs and two
common activelow Output Enables. When either of the enables is
high, the buffer outputs are placed into highimpedance states. The
HCT366A has inverting outputs.
Features
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 90 FETs or 22.5 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECQ100
Qualified and PPAP Capable
These are PbFree Devices*
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
MARKING
DIAGRAMS
SOIC16
D SUFFIX
CASE 751B
TSSOP16
DT SUFFIX
CASE 948F
1
16
1
16
1
16
HCT366AG
AWLYWW
HCT
366A
ALYWG
G
1
16
A = Assembly Location
WL, L = Wafer Lot
Y = Year
WW, W = Work Week
G or G = PbFree Package
(Note: Microdot may be in either location)
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
MC74HCT366A
http://onsemi.com
2
Figure 1. Pin Assignment
Figure 2. Logic Diagram
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
A4
Y5
A5
OUTPUT
ENABLE 2
V
CC
Y3
A3
Y4
A1
Y0
A0
OUTPUT
ENABLE 1
GND
Y2
A2
Y1
A3
A4
A5
A0
A1
A2
2
4
6
10
12
14
OUTPUT ENABLE 1
1
15
PIN 16 = V
CC
PIN 8 = GND
OUTPUT ENABLE 2
Y3
Y4
Y5
Y0
Y1
Y2
3
5
7
9
11
13
FUNCTION TABLE
X = don’t care
Z = high impedance
Inputs Output
Enable
1
Enable
2AY
L
L
H
X
L
L
X
H
L
H
X
X
H
L
Z
Z
ORDERING INFORMATION
Device Package Shipping
MC74HCT366ADG
SOIC16
(PbFree)
48 Units / Rail
MC74HCT366ADR2G 2500 Units / Reel
MC74HCT366ADTR2G
TSSOP16
(PbFree)
2500 Units / Reel
NLVHCT366ADTRG* 2500 Units / Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AECQ100 Qualified and PPAP
Capable.
MC74HCT366A
http://onsemi.com
3
MAXIMUM RATINGS*
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V
V
in
DC Input Voltage (Referenced to GND) – 0.5 to V
CC
+ 0.5 V
V
out
DC Output Voltage (Referenced to GND) – 0.5 to V
CC
+ 0.5 V
I
in
DC Input Current, per Pin ± 20 mA
I
out
DC Output Current, per Pin ± 25 mA
I
CC
DC Supply Current, V
CC
and GND Pins ± 50 mA
P
D
Power Dissipation in Still Air, SOIC Package†
TSSOP Package†
500
450
mW
T
stg
Storage Temperature – 65 to + 150
_C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
Derating SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage (Referenced to GND) 2.0 6.0 V
V
in
, V
out
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
CC
V
T
A
Operating Temperature, All Package Types – 55 + 125
_C
t
r
, t
f
Input Rise and Fall Time V
CC
= 2.0 V
(Figure 1) V
CC
= 3.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
0
0
0
0
1000
600
500
400
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not
implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may
affect device reliability.
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter Test Conditions
V
CC
V
Guaranteed Limit
Unit
– 55 to
25_C
v 85_C v 125_C
V
IH
Minimum HighLevel Input
Voltage
V
out
= V
CC
– 0.1 V
|I
out
| v 20 μA
4.5
to
5.5
2.0 2.0 2.0 V
V
IL
Maximum LowLevel Input
Voltage
V
out
= 0.1 V
|I
out
| v 20 μA
4.5
to
5.5
0.80 0.80 0.80 V
V
OH
Minimum HighLevel Output
Voltage
V
in
= V
IH
|I
out
| v 20 μA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
in
= V
IH
|I
out
| v 3.6 mA
|I
out
| v 6.0 mA
|I
out
| v 7.8 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
V
OL
Maximum LowLevel Output
Voltage
V
in
= V
IL
|I
out
| v 20 μA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
= V
IL
|I
out
| v 3.6 mA
|I
out
| v 6.0 mA
|I
out
| v 7.8 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
I
in
Maximum Input Leakage Current V
in
= V
CC
or GND 6.0 ± 0.1 ± 1.0 ± 1.0 μA
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.

MC74HCT366ADTG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Buffers & Line Drivers IC BUFF DVR TRI-ST HEX
Lifecycle:
New from this manufacturer.
Delivery:
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