NCN5192
http://onsemi.com
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clock frequency of 460.8 kHz. CS is clocked in at the falling
edge of the CLK1 clock to detect if the data is for the mode
register or the DAC.
SCLK can begin to clock in DATA serially to the chip on
the falling edge of SCLK. SCLK should have a maximum
frequency of 460.8 kHz. The format of the data should be
either 8 or 16 bits with the most significant bit first.
DATA is shifted into the chip on the falling edge of SCLK,
and thus for correct operation DATA should change only on
the rising edge of SCLK. The first bit shifted in is the MSB.
If 14 bit DAC communication is utilized, then two 0’s should
precede the 14 bits, and 16 clock cycles on SCLK should
occur. Once the data is shifted in, CS should go low no
sooner than one clock cycle after the last rising edge of
SCLK.
Table 9. INTERNAL REGISTER DESCRIPTION
Bit Description
0 (LSB) 0 = DAC in 14−bit mode
1 = DAC in 16−bit mode
1
Set the crystal divide so that CLK2 is 460.8 kHz
Bit 2 Bit 1
0 0 Crystal/2
0 1 Crystal/4
1 0 Crystal/1
1 1 Crystal/4
2
3
Set the crystal divide for CLK1
Bit 4 Bit 3
0 0 Crystal/2
0 1 Crystal/4
1 0 Crystal/1
1 1 Crystal/4
4
5 0 = Watchdog kick external (pin)
1 = Watchdog kick internal (1.8 kHz)
6 0 = RTZ output format on DAC
1 = Non RTZ output format on DAC
7 (MSB) 0 = RxD is low when carrier is off
1 = RxD is high when carrier is off
Setting this bit, changes the function of RxD to
the function of RxD_ENH
Internal Register
The NCN5192 has an 8 bit register to setup its internal
operation. An 8 bit SPI communication method is used to
write to the mode register. If CS goes low after only 8 clock
cycles of SCLK the Mode register will latch in the 8 bits
which are shifted into the SPI shift register. In Table 9 an
explanation of the usage of each bit is given. All bits are set
to ‘0’ at reset.
Sigma Delta DAC
The NCN5192 Modem has an integrated Sigma−Delta
Modulator for use in a current loop slave transmitter.
Through this DAC, an analog value can be set and
transmitted across the current loop. For more information on
how to create a current loop slave transmitter, see
application notes on the ON Semi website. The DAC output
will switch between 0 V and the voltage provided to
DACREF. To achieve maximum accuracy, the DACREF
voltage should be kept stable, so that power supply
variations are not visible in the DAC output. The
Sigma−Delta modulator output can be set through SPI
frames containing 14 or 16 significant bits. The length of the
data frames can be set through bit 0 is the status register. The
output of the DAC can be set return to zero (RTZ) or
non−RTZ. This is important when the rise and fall time of the
signal are not identical. This will cause a DC offset
depending on the number of rising and falling edges. As the
output bits of a sigma−delta modulator are randomly
arranged (ie. for the same setting we could get 01110000 or
01010100), the number of edges might vary over time for a
non return to zero signal. Setting the DAC to “return to zero”
forces the output to have a rising and falling edge for each
logic “1” bit, so that no offset from pulse asymmetry can
occur. However, this will decrease the range of the
modulator to 50% of DACREF, as the maximum duty cycle
is 50% instead of 100% for NRZ. When a clock failure is
detected, using an internal oscillator, the DAC output will
jump to the level set by the JUMP pin, until the IC is reset
or a rising flank is detected on KICK.
Table 10. SPI FRAME FORMAT
Description Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mode Register 8 Mode Register Data
DAC – 14 bits mode 16 0 0 DAC Output Word
DAC – 16 bits mode 16 DAC Output Word
