NCN5192MNRG Datasheet NCN5192MNRG, NCN5192MNG, NCN5192GEVB | P7-P9

NCN5192

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Pin Descriptions

Table 8. PIN DESCRIPTIONS

Symbol Pin Name Description

AREF Analog reference voltage Receiver Reference Voltage. Normally 1.23 V is selected (in combination with VDDA

= 3.3 V). See Table 2.

CDREF Carrier detect reference voltage Carrier Detect Reference voltage. The value should be 85 mV below AREF to set

the carrier detection to a nominal of 100 mV

p−p

RESETB Reset digital logic When at logic low (V

) this input holds all the digital logic in reset. During normal

operation RESETB should be at V

RTSB Request to send Active−low input selects the operation of the modulator. TxA is enabled when this

signal is low. This signal must be held high during power−up.

RxA Analog receive input Receive Data Demodulator Input. Accepts a HART 1200 / 2200 Hz FSK modulated

waveform as input.

RxAFI Analog receive comparator input Positive input of the carrier detect comparator and the receiver filter comparator.

TxD Digital transmit input Input to the modulator accepts digital data in NRZ form. When TxD is low, the modu-

lator output frequency is 2200 Hz. When TxD is high, the modulator output frequency

is 1200 Hz.

XIN Oscillator input Input to the internal oscillator must be connected to a parallel mode ceramic resonator

when using the internal oscillator or grounded when using an external clock signal.

XOUT Oscillator output Output from the internal oscillator must be connected to an external clock signal or to

a parallel mode ceramic resonator when using the internal oscillator.

CLK1 Programmable Clock Output Output signal derived from oscillator output, frequency division set by internal register.

CLK2 Programmable Clock Output Output signal derived from oscillator output, frequency division set by internal register.

As this signal is also used internally, the division should be set so that the output fre-

quency is 460.8 kHz

CBIAS Comparator bias current Connection to the external bias resistor. R

BIAS

should be selected such that AREF /

BIAS

= 2.5 mA ± 5 %

CD Carrier detect output Output goes high when a valid input is recognized on RxA. If the received signal is

greater than the threshold specified on CDREF for four cycles of the RxA signal, the

valid input is recognized.

RxAF Analog receive filter output The output of the three pole high pass receive data filter

RxD Digital receive output Signal outputs the digital receive data. When the received signal (RxA) is 1200 Hz,

RxD outputs logic high. When the received signal (RxA) is 2200 Hz, RxD outputs

logic low. The HART receive data stream is only active if Carrier Detect (CD) is high.

RxD_ENH Digital receive output, alternative Not(OCD) or RXD

TxA Analog transmit output Transmit Data Modulator Output. A trapezoidal shaped waveform with a frequency of

1200 Hz or 2200 Hz corresponding to a data value of 1 or 0 respectively applied to

TxD. TxA is active when RTSB is low. TxA equals 0.5 V when RTSB is high.

SCLK SPI bus clock line Serial communication clock line

DATA SPI bus data line Serial communication data line. Frames transmitted can either be 8 bit or 16 bit long.

CS SPI bus chip select Serial communication chip select line. Pulled high by microcontroller while a frame is

transmitted.

JUMP DAC Alarm value When a problem is detected, such as a clock failure or the watchdog going off, the

DAC will jump to VSS or DACREF, depending on whether this pin is connected to

VSS or VDD respectively.

DACREF DAC Reference This is the high value of the output and can be connected to any voltage between

AREF and VDD.

DAC DAC Output Output of a 16 bit Sigma−Delta Modulator

KICK Watchdog Kick Periodically a pulse should be provided to reset the watchdog. This can be configured

in internal registers for an internal 1.8kHz signal, or to an external signal provided to

this pin.

VPOR POR Input Input to the POR comparator. The voltage on this pin is compared with AREF. An

external resistor divider should divide the supply voltage to this pin.

VDD Digital power Power for the digital modem circuitry

VDDA Analog supply voltage Power for the analog modem circuitry

VSS Ground Digital ground

VSSA Analog ground Analog ground

NCN5192

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Functional Description

The NCN5192 is a single-chip modem for use in Highway

Addressable Remote Transducer (HART) field instruments

and masters. The modem IC contains a transmit data

modulator with signal shaper, carrier detect circuitry, an

analog receiver, demodulator circuitry and an oscillator, as

shown in the block diagram in Figure 1.

The modulator accepts digital data at its digital input TxD

and generates a trapezoidal shaped FSK modulated signal at

the analog output TxA. A digital “1” or mark is represented

with a frequency of 1200 Hz. A digital “0” or space is

represented with a frequency of 2200 Hz. The used bit rate

is 1200 baud.

The demodulator receives the FSK signal at its analog

input, filters it with a band-pass filter and generates 2 digital

signals: RxD: Received Data and CD: Carrier Detect. At the

digital output RxD the original modulated signal is received.

CD outputs the Carrier Detect signal. It goes logic high if the

received signal is above 100 mVpp during 4 consecutive

carrier periods.

The oscillator provides the modem with a stable time base

using either a simple external resonator or an external clock

source.

Detailed Description

Modulator

The modulator accepts digital data in NRZ form at the

TxD input and generates the FSK modulated signal at the

TxA output.

PC20101117.1

Sine

Shaper

Numeric

Controlled

Oscillator

MODULATOR

TxA

TxD

RTS

FSK_OUT

Figure 4. Modulator Block Diagram

A logic “1” or mark is represented by a frequency f

1200 Hz. A logic “0”or space is represented by a frequency

= 2200 Hz.

BIT

833

“1” = Mark

1.2 kHz

“0” = Space

2.2 kHz

KVDE20110407.5

BIT

= 454 ms

Figure 5. Modulation Timing

The Numeric Controlled Oscillator (NCO) works in a

phase continuous mode preventing abrupt phase shifts when

switching between mark and space frequency. The control

signal “Request To Send” (RTSB) enables the NCO. When

RTSB is logic low the modulator is active and NCN5192 is

in transmit mode. When RTSB is logic high the modulator

is disabled and NCN5192 is in receive mode.

The digital outputs of the NCO are shaped in the Wave

Shaper block to a trapezoidal signal. This circuit controls the

rising and falling edge to be inside the standard HART

waveshape limits. Figure 6 shows the transmit-signal forms

captured at TxA for mark and space frequency. The slew

rates are SR

= 1860 V/s at the mark frequency and SR

3300 V/s at the space frequency. For AREF = 1.235 V, TxA

will have a voltage swing from approximately 0.25 to

0.75 V

t (ms)

TxA

0.5 V

t (ms)

TxA

“1” = Mark; f

=1.2 kHz

“0” = Space; f

=2.2 kHz

KVDE2011040

= 1860 V/s

0.5 V

= 3300 V/s

0.5 V

Figure 6. Modulator shaped output signal for Mark

and Space frequency at TxA pin.

Demodulator

The demodulator accepts a FSK signal at the RxA input

and reconstructs the original modulated signal at the RxD

output. Figure 7 illustrates the demodulation process.

BIT

IDLE (mark)

LSB MSB IDLE (mark)

BIT

8 data bits

D0Start D1 D2 D3 D4 D5 D6

D7 Stop

Par

“0” “1” “0” “1” “0” “1”“0” “0”“0” “1”

FSK_IN

RxD

PC20101013.4

Figure 7. Modulation Timing

This HART bit stream follows a standard 11-bit UART

frame with Start, Stop, 8 Data – and 1 Parity bit (odd). The

communication speed is 1200 baud.

NCN5192

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Receive Filter and Comparator

The received FSK signal first is filtered using a band-pass

filter build around the low noise receiver operational

amplifier “Rx HP filter”. This filter blocks interferences

outside the HART signal band.

Rx Comp

Rx HP Filter

RxAF

RxA

RxAFI

AREF

DEMODULATOR

HART IN

1.235 V

PC20101118.2

15 MW

Figure 8. Demodulator Receive Filter and Signal

Comparator

The filter output is fed into the Rx comparator. The

threshold value equals the analog ground making the

comparator to toggle on every zero crossing of the filtered

FSK signal. The maximum demodulator jitter is 12 % of one

bit given the input frequencies are within the HART

specifications, a clock frequency of 460.8 kHz (±1.0 %) and

zero input (RxA) asymmetry.

Carrier Detect Circuitry

Low HART input signal levels increases the risk for the

generation of bit errors. Therefore the minimum signal

amplitude is set to 80−120 mVpp. If the received signal is

below this level the demodulator is disabled.

This level detection is done in the Carrier Detector. The

output of the demodulator is qualified with the carrier detect

signal (CD), therefore, only RxA signals large enough to be

detected (100 mV

p-p

typically) by the carrier detect circuit

produce received serial data at RxD.

Figure 9. Demodulator Carrier and Signal

Comparator

RxD

Demodulator

Logic

Rx Comp

Carrier Detect

Counter

Carrier Comp

DEMODULATOR

RxAFI

AREF

CDREF

15 MW

FILTERED

HART IN

1.235 V

AREF

–80mV

KVDE20110407.6

RxD_ENH

The carrier detect comparator shown in Figure 9 generates

logic low output if the RxAFI voltage is below CDREF. The

comparator output is fed into a carrier detect block. The

carrier detect block drives the carrier detect output pin CD

high if RTSB is high and four consecutive pulses out of the

comparator have arrived. CD stays high as long as RTSB is

high and the next comparator pulse is received in less than

2.5 ms. Once CD goes inactive, it takes four consecutive

pulses out of the comparator to assert CD again. Four

consecutive pulses amount to 3.33 ms when the received

signal is 1200 Hz and to 1.82 ms when the received signal

is 2200 HZ. The difference between RxD and RxD_ENH is

evident when CD is low: RxD is then also low, while

RxD_ENH is then high. When CD is high, RxD and

RxD_ENH have the same output.

Miscellaneous Analog Circuitry

Voltage References

The NCN5192 requires two voltage references, AREF

and CDREF. AREF sets the DC operating point of the

internal operational amplifiers and is the reference for the

Rx comparator. If NCN5192 operates at V

= 3.3 V the ON

Semiconductor LM285D 1.235 V reference is

recommended.

The level at which CD (Carrier Detect) becomes active is

determined by the DC voltage difference (CDREF - AREF).

Selecting a voltage difference of 80 mV will set the carrier

detect to a nominal 100 mV

p-p

Bias Current Resistor

The NCN5192 requires a bias current resistor R

BIAS

to be

connected between CBIAS and V

. The bias current

controls the operating parameters of the internal operational

amplifiers and comparators and should be set to 2.5 mA.

BIAS

CBIAS

OPA

AREF

2. 5 mA

BIAS

PC20101118 .4

Figure 10. Bias Circuit

The value of the bias current resistor is determined by the

reference voltage AREF and the following formula:

BIAS

AREF

2.5 mA

The recommended bias current resistor is 500 KW when

AREF is equal to 1.235 V.

Oscillator

The clock signal used by NCN5192 can either be

460.8 kHz, 921.6 kHz or 1.8432 MHz. This can be provided

by an external clock or a resonator or crystal connected to the

internal oscillator.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P13

NCN5192MNRG

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Manufacturer:

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Description:

Interface - Specialized A5191HRTLG HART MODEM

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NCN5192MNRG

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