NCP451AFCT2G

© Semiconductor Components Industries, LLC, 2015
July, 2015 − Rev. 9
1 Publication Order Number:
NCP451/D
NCP451
3A Ultra-Small Low Ron
and Controlled Load Switch
with Auto-Discharge Path
The NCP451 is a very low Ron MOSFET controlled by external
logic pin, allowing optimization of battery life, and portable device
autonomy.
Indeed, due to a current consumption optimization with NMOS
structure, leakage currents are eliminated by isolating connected IC on
the battery when not used.
Output discharge path is also embedded to eliminate residual
voltages on the output rail.
Proposed in a wide input voltage range from 0.75 V to 5.5 V, in a
small 0.9 x 1.4 mm WLCSP6, pitch 0.5 mm.
Features
0.75 V – 5.5 V Operating Range
12 mW N MOSFET from 3.6 V to 5.5 V
13 mW N MOSFET from 1 V to 3.3 V
DC Current Up to 3 A
Output Auto−Discharge
Active High EN Pin
WLCSP6 0.9 x 1.4 mm
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
Mobile Phones
Tablets
Digital Cameras
GPS
Portable Devices
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See detailed ordering, marking and shipping information on
page 10 of this data sheet.
ORDERING INFORMATION
(Top View)
PINOUT DIAGRAM
A
B
C
12
OUT IN
OUT IN
GND EN
WLCSP6
FC SUFFIX
CASE 499BR
MARKING
DIAGRAM
XXXXG
AYWW
XXXX = Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
WLCSP6
AFC SUFFIX
CASE 567KB
XXXXG
AYWW
NCP451
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2
ENx
EN
0
DCDC Converter
V+
Platform IC’n
LS
LDO
or
NCP451
IN
A2
IN
B2
GND
C1
EN
C2
OUT
B1
OUT
A1
Figure 1. Typical Application Circuit
PIN FUNCTION DESCRIPTION
Pin Name Pin Number Type Description
IN A2, B2 POWER
Load−switch input voltage; connect a 1 mF or greater ceramic capacitor from IN to GND as
close as possible to the IC.
GND C1 POWER Ground connection.
EN C2 INPUT Enable input, logic high turns on power switch.
OUT A1, B1 OUTPUT
Load−switch output; connect a 1 mF ceramic capacitor from OUT to GND as close as
possible to the IC is recommended.
BLOCK DIAGRAM
EN Block
Control
logic
Charge Pump and
soft start control
IN: Pin A2, B2
EN: Pin C2
OUT: Pin A1, B1
GND: Pin C1
Figure 2. Block Diagram
NCP451
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3
MAXIMUM RATINGS
Symbol Rating Value Unit
IN, OUT, EN, Pins: (Note 1) V
EN,
V
IN,
V
OUT
−0.3 to + 7.0 V
From IN to OUT Pins: Input/Output (Note 1) V
IN,
V
OUT
0 to + 7.0 V
Human Body Model (HBM) ESD Rating are (Notes 1 and 2) ESD HBM 1.5 kV
Machine Model (MM) ESD Rating are (Notes 1 and 2) ESD MM 250 V
Charge Device Model (CDM) ESD Rating are (Notes 1 and 2) ESD CDM 2000 V
Latch−up protection (Note 3)
−Pins IN, OUT, EN
LU 100 mA
Maximum Junction Temperature T
J
−40 to + 125 °C
Storage Temperature Range T
STG
−40 to + 150 °C
Moisture Sensitivity (Note 4) MSL Level 1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. According to JEDEC standard JESD22−A108.
2. This device series contains ESD protection and passes the following tests:
Human Body Model (HBM) ±1.5 kV per JEDEC standard: JESD22−A114 for all pins.
Machine Model (MM) ±250 V per JEDEC standard: JESD22−A115 for all pins.
Charge Device Model (CDM) ±2.0 kV per JEDEC standard: JESD22−C101 for all pins.
3. Latchup Current Maximum Rating: ±100 mA per JEDEC standard: JESD78 class II.
4. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020.
OPERATING CONDITIONS
Symbol Parameter Conditions Min Typ Max Unit
V
IN
Operational Power Supply 0.75 5.5 V
V
EN
Enable Voltage 0 5.5 V
T
A
Ambient Temperature Range −40 25 +85 °C
T
J
Junction Temperature Range −40 25 +125 °C
C
IN
Decoupling input capacitor 1
mF
C
OUT
Decoupling output capacitor 1
mF
R
q
JA
Thermal Resistance Junction to Air (Note 5) 100 °C/W
I
OUT
Maximum DC current 3 A
P
D
Power Dissipation Rating (Note 6) Over temperature 0.315 W
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
5. The R
q
JA
is dependent of the PCB heat dissipation and thermal via.
6. The maximum power dissipation (P
D
) is given by the following formula:
P
D
+
T
JMAX
* T
A
R
qJA

NCP451AFCT2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Power Switch ICs - Power Distribution 3A LOW RON LOAD SWITCH WI
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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