NCP451AFCT2G

NCP451
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7
ELECTRICAL CURVES
Figure 10. EN Pin Leakage vs. Temperature
V
EN
= V
IN
= 5.5 V
V
EN
= V
IN
= 3.6 V
JUNCTION TEMPERATURE (°C)
I
ENleak
(nA)
−50
4
2
0
−25 0 25 12510050 75
NCP451
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8
FUNCTIONAL DESCRIPTION
Overview
The NCP451 is a high side N channel MOSFET power
distribution switch designed to isolate ICs connected on the
battery in order to save energy. The part can be turned on,
with a wide range of battery from 0.75 V to 5.5 V.
Enable Input
Enable pin is an active high. The path is opened when EN
pin is tied low (disable), forcing N−MOSFET switch off.
The IN/OUT path is activated with a minimum of Vin of
0.75 V and EN forced to high level.
Auto Discharge
N−MOSFET is placed between the output pin and GND,
in order to discharge the application capacitor connected on
OUT pin.
The auto−discharge is activated when EN pin is set to low
level (disable state).
The discharge path (Pull down NMOS) stays activated as
long as EN pin is set at low level and V
IN
> 0.75 V.
In order to limit the current across the internal discharge
N−MOSFET, the typical value is set at R
DIS
.
C
IN
and C
OUT
Capacitors
IN and OUT, 1 mF, at least, capacitors must be placed as
close as possible the part to for stability improvement.
APPLICATION INFORMATION
Power Dissipation
Main contributor in term of junction temperature is the
power dissipation of the power MOSFET. Assuming this,
the power dissipation and the junction temperature in
normal mode can be calculated with the following
equations:
P
D
+ R
DS(on)
ǒ
I
OUT
Ǔ
2
P
D
= Power dissipation (W)
R
DS(on)
= Power MOSFET on resistance (W)
I
OUT
= Output current (A)
T
J
+ P
D
R
qJA
) T
A
T
J
= Junction temperature (°C)
R
q
JA
= Package thermal resistance (°C/W)
T
A
= Ambient temperature (°C)
PCB Recommendations
The NCP451 integrates an up to 3 A rated NMOS FET,
and the PCB design rules must be respected to properly
evacuate the heat out of the silicon. By increasing PCB area,
especially around IN and OUT pins, the R
q
JA
of the package
can be decreased, allowing higher power dissipation.
Routing example: 2 oz, 4 layers with vias across 2 internal
inners.
Figure 11.
Example of application definition.
T
J
* T
A
+ R
qJA
R
DS(on)
I
2
T
J
: junction temperature.
T
A
: ambient temperature.
Rtheta= Thermal resistance between IC and air, through
PCB.
R
DS(on)
: intrinsic resistance of the IC MOSFET.
I: load DC current.
NCP451
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9
Taking into account of Rtheta obtain with:
1 oz, 2 layers: 100°C/W.
At 3 A, 25°C ambient temperature, R
DS(on)
20 mW @ V
IN
5 V, the junction temperature will be:
T
J
* T
A
+ Rtheta P
D
+ 25 )
ǒ
0.02 3
3
Ǔ
100 + 43° C
Taking into account of Rtheta obtain with:
2 oz, 4 layers: 60°C/W.
At 3 A, 65°C ambient temperature, R
DS(on)
24 mW @ V
IN
5 V, the junction temperature will be:
T
J
+ T
A
) Rtheta P
D
+ 65 )
ǒ
0.024 3
2
Ǔ
60 + 78° C
Figure 12. Demoboard PCB Top View
Figure 13. Demoboard PCB Top View
OUT2
GND
12
INPUT2
C1
EN
OUT1
GND
12
D1
DIODE ZENER1
D2
DIODE ZENER1
INPUT1
R1
100 k
R2
100 k
C2
GND1
GND
GND2
GND3
U1
NCP451
IN
A2
IN
B2
GND
C1
EN
C2
OUT
B1
OUT
A1
Figure 14. Demobard schematic

NCP451AFCT2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Power Switch ICs - Power Distribution 3A LOW RON LOAD SWITCH WI
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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