Philips Semiconductors Preliminary specification
XA-C3
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
2000 Jan 25
30
t
PXIZ
ALE
PSEN
MULTIPLEXED
ADDRESS AND DATA
UNMULTIPLEXED
ADDRESS
A1–A3
t
AVLL
t
PXIX
t
LLAX
INSTR IN *
t
LHLL
t
PLPH
t
PLAZ
t
LLPL
t
AVIVA
SU00946
t
PLIV
A4–A19
t
IXUA
* D0–D15
Figure 21. External PROGRAM Memory Read Cycle (ALE Cycle)
ALE
PSEN
MULTIPLEXED
ADDRESS AND DATA
UNMULTIPLEXED
ADDRESS
A1–A3
INSTR IN
*
SU01345
A4–A19
t
AVIVB
* D0–D15
A1–A3
Figure 22. External PROGRAM Memory Read Cycle (Non-ALE Cycle)
Philips Semiconductors Preliminary specification
XA-C3
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
2000 Jan 25
31
ALE
MULTIPLEXED
ADDRESS
AND DATA
UNMULTIPLEXED
ADDRESS
RD
DATA IN *
A4–A19
A1–A3
t
LLRL
t
RLRH
t
LLAX
t
AVLL
t
RHDX
t
RHDZ
t
AVDVA
t
RLDV
SU01346
t
DXUA
* D0–D15
Figure 23. External DATA Memory Read Cycle (ALE Cycle)
t
UAWH
t
LLAX
ALE
MULTIPLEXED
ADDRESS
AND DATA
UNMULTIPLEXED
ADDRESS
WRL
or WRH
A4–A19
DATA OUT
*
A1–A3
t
LLWL
t
WLWH
t
AVLL
t
AVWL
t
QVWX
t
WHQX
SU01347
* D0–D15
Figure 24. External DATA Memory Write Cycle
Philips Semiconductors Preliminary specification
XA-C3
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
2000 Jan 25
32
XTAL1
ADDRESS BUS
WAIT
SU00709A
t
WTL
ALE
BUS STROBE
(WRL, WRH,
RD, OR PSEN)
t
WTH
t
CRAR
(The dashed line shows the strobe without WAIT.)
Figure 25. WAIT Signal Timing
V
DD
–0.5
0.45V
0.7V
DD
0.2V
DD
–0.1
t
CHCL
t
C
t
CLCH
t
CLCX
t
CHCX
SU00842
Figure 26. External Clock Drive
V
DD
–0.5
0.45V
0.2V
DD
+0.9
0.2V
DD
–0.1
NOTE:
AC inputs during testing are driven at V
DD
–0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.
Timing measurements are made at the 50% point of transitions.
SU00703A
Figure 27. AC Testing Input/Output
V
LOAD
V
LOAD
+0.1V
V
LOAD
–0.1V
V
OH
–0.1V
V
OL
+0.1V
NOTE:
TIMING
REFERENCE
POINTS
For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs,
and begins to float when a 100mV change from the loaded V
OH
/V
OL
level occurs. I
OH
/I
OL
±20mA.
SU00011
Figure 28. Float Waveform

PXAC37KFA/00,512

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC MCU 16BIT 32KB OTP 44PLCC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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