Philips Semiconductors Preliminary specification
XA-C3
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
2000 Jan 25
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must be readable by the processor as an MMR. If the processor is
about to put the part into power–down mode, it must read this bit
first to determine if it is safe to do so. There is no need for the
processor to read this bit prior to entering idle mode. The core is free
to go into idle mode whenever it chooses. The CAN/CTL module will
follow if and when it is ready. All of the logic required to implement
everything discussed in this section will be in the CCB.
MEMORY INTERFACE UNIT
General Description
The XA-C3 memory interface (MIF) unit provides interfaces to
generic memory devices such as SRAM, flash, and EPROM. The
timing of memory cycles, including different strobe widths, is
programmable by software.
MIF arbitrates between memory accesses from the XA core and
from the DMA unit associated with the CAN/CTL function. It also
provides access to the on–chip Memory Mapped Registers (MMRs)
and the on–chip message buffer RAM (XRAM).
Summary of features
D Supports generic memory including SRAM, flash, and EPROM.
D Programmable timing.
D Supports wait states.
D Static 16-bit bus sizing.
D Arbitrates between CPU and DMA access.
D Relocatable Memory Mapped Register (MMR) access for
CAN/CTL related configuration and data.
Memory Mapped Registers (MMRs)
The XA-C3 has several hundred bytes of memory mapped
control/status registers (MMRs). These registers are mapped to the
main data memory space. A 4KByte space is reserved from the data
memory space for memory mapped registers (MMRs).
The base address of the MMR space is programmed by software. It
can be placed anywhere within the entire 16 MByte data memory
space supported by the XA architecture, other than at the very
bottom of memory (address 000000h) where it would conflict with
the on–chip DATA RAM (Scratch Pad). The 4K MMR space will
always start at a 4K boundary.
The base address of the MMR space is determined by the contents
of Special Function Registers MRBL and MRBH, as shown in Table
6 on page 11. Any address asserted by the XA whose twelve most
significant bits match the concatenation MRBH[7:0] MRBL[7:4] will
be automatically routed to the on–chip MMR bus.
The reset values for MRBH and MRBL are 0Fh and F0h
respectively. Therefore, after a reset the MMR space is mapped to
the uppermost 4K bytes of Data Segment 0Fh, but access to MMRs
is
disabled
. The first 512 Bytes (offset 000h – 1FFh) of MMR Space
are the Message Object Registers (eight per Message Object) for
objects n = 0 – 31, as shown in Figure
MMR
Space
4K bytes
Segment xy in Data
Memory Space (DS = xy)
MRBL[7:4]0000MRBH[7:0] 00h
a23 a16 a15 a0a7a8
xyFFFFh
xy0000h
SU01340
Figure 43. Formation of the MMR Base Address
