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AT45DB011B-CC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
1
1-megabit
2.7-volt Only
DataFlash
®
AT45DB011B
Features
• Single 2.7V - 3.6V Supply
• Serial Peripheral Interface (SPI) Compatible
• 20 MHz Max Clock Frequency
• Page Program Operation
– Single Cycle Reprogram (Erase and Program)
– 512 Pages (264 Bytes/Page) Main Memory
• Supports Page and Block Erase Operations
• One 264-byte SRAM Data Buffer
• Continuous Read Capability through Entire Array
– Ideal for Code Shadowing Applications
• Fast Page Program Time – 7 ms Typical
• 120 µs Typical Page to Buffer Transfer Time
• Low Power Dissipation
– 4 mA Active Read Current Typical
– 2 µA CMOS Standby Current Typical
• Hardware Data Protection Feature
• 100% Compatible with AT45DB011
• Commercial and Industrial Temperature Ranges
• Green (Pb/Halide-free/RoHS Compliant) Packaging Options
Description
The AT45DB011B is a 2.7-volt only, serial interface Flash memory ideally suited for
a wide variety of digital voice-, image-, program code- and data-storage applications.
Its 1,081,344 bits of memory are organized as 512 pages of 264 bytes each. In addi-
tion to the main memory, the AT45DB011B also contains one SRAM data buffer of 264
bytes. The buffer allows receiving of data while a page in the main memory is being
reprogrammed. EEPROM emulation (bit or byte alterability) is easily handled with a
self-contained three step Read-Modify-Write operation. Unlike conventional Flash
memories that are accessed randomly with multiple address lines and a parallel inter-
face, the DataFlash uses a SPI serial interface to sequentially access its data. SPI
mode 0 and mode 3 are supported. The simple serial interface facilitates hardware
AT45DB011B
Preliminary 16-
Megabit 2.7-volt
Only Serial
DataFlash
Pin Configurations
Pin Name Function
CS
Chip Select
SCK Serial Clock
SI Serial Input
SO Serial Output
WP Hardware Page
Write Protect Pin
RESET
Chip Reset
RDY/BUSY
Ready/Busy
CBGA Top View
through Package
A
B
C
123
VCC
WP
RESET
GND
RDY/BSY
SI
SCK
CS
SO
TSSOP Top View
Ty p e 1
1
2
3
4
5
6
7
14
13
12
11
10
9
8
RDY/BUSY
RESET
WP
VCC
GND
SCK
SO
CS
NC
NC
NC
NC
NC
SI
SOIC
1
2
3
4
8
7
6
5
SI
SCK
RESET
CS
SO
GND
VCC
WP
1984J–DFLASH–06/06
2
AT45DB011B
1984J–DFLASH–06/06
layout, increases system reliability, minimizes switching noise, and reduces package size and
active pin count. The device is optimized for use in many commercial and industrial applica-
tions where high density, low pin count, low voltage, and low power are essential. The device
operates at clock frequencies up to 20 MHz with a typical active read current consumption of
4mA.
To allow for simple in-system reprogrammability, the AT45DB011B does not require high input
voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for
both the program and read operations. The AT45DB011B is enabled through the chip select
pin (CS
) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Out-
put (SO), and the Serial Clock (SCK).
All programming cycles are self-timed, and no separate erase cycle is required before
programming.
When the device is shipped from Atmel, the most significant page of the memory array may
not be erased. In other words, the contents of the last page may not be filled with FFH.
Block Diagram
Memory Array
To provide optimal flexibility, the memory array of the AT45DB011B is divided into three levels
of granularity comprising of sectors, blocks, and pages. The Memory Architecture Diagram
illustrates the breakdown of each level and details the number of pages per sector and block.
All program operations to the DataFlash occur on a page by page basis; however, the optional
erase operations can be performed at the block or page level.
FLASH MEMORY ARRAY
PAGE (264 BYTES)
BUFFER (264 BYTES)
I/O INTERFACE
SCK
CS
RESET
VCC
GND
RDY/BUSY
WP
SOSI
3
AT45DB011B
1984J–DFLASH–06/06
Memory Architecture Diagram
Device
Operation
The device operation is controlled by instructions from the host processor. The list of instruc-
tions and their associated opcodes are contained in Tables 1 through 4 (pages 11 and 12). A
valid instruction starts with the falling edge of CS
followed by the appropriate 8-bit opcode and
the desired buffer or main memory address location. While the CS
pin is low, toggling the SCK
pin controls the loading of the opcode and the desired buffer or main memory address location
through the SI (serial input) pin. All instructions, addresses, and data are transferred with the
most significant bit (MSB) first.
Buffer addressing is referenced in the datasheet using the terminology BFA8-BFA0 to denote
the nine address bits required to designate a byte address within a buffer. Main memory
addressing is referenced using the terminology PA8-PA0 and BA8-BA0 where PA8-PA0
denotes the 10 address bits required to designate a page address and BA8-BA0 denotes the
nine address bits required to designate a byte address within the page.
Read Commands By specifying the appropriate opcode, data can be read from the main memory or from the
data buffer. The DataFlash supports two categories of read modes in relation to the SCK sig-
nal. The differences between the modes are in respect to the inactive state of the SCK signal
as well as which clock cycle data will begin to be output. The two categories, which are com-
prised of four modes total, are defined as Inactive Clock Polarity Low or Inactive Clock Polarity
High and SPI Mode 0 or SPI Mode 3. A separate opcode (refer to Table 1 on page 11 for a
complete list) is used to select which category will be used for reading. Please refer to the
“Detailed Bit-level Read Timing” diagrams in this datasheet for details on the clock cycle
sequences for each mode.
Block = 2112 bytes
(2K + 64)
8 Pages
BLOCK 0
BLOCK 1
BLOCK 2
BLOCK 62
BLOCK 63
BLOCK 61
Page = 264 bytes
(256 + 8)
PAGE 0
PAGE 1
PAGE 6
PAGE 7
PAGE 8
PAGE 9
PAGE 510
PAGE 511
BLOCK 0
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
PAGE 509
BLOCK 1
BLOCK ARCHITECTURE PAGE ARCHITECTURE
SECTOR 0 = 2112 BYTES (2K + 64)
SECTOR 1 = 65,472 BYTES (62K + 1984)
SECTOR ARCHITECTURE
SECTOR 2 = 67,584 BYTES (64K + 2K)
BLOCK 3
BLOCK 29
BLOCK 30
BLOCK 31
BLOCK 32
BLOCK 33
BLOCK 34
SECTOR 1SECTOR 2
SECTOR 0
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32

AT45DB011B-CC

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IC FLASH 1M SPI 20MHZ 9CBGA
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