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AT45DB011B-CC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
4
AT45DB011B
1984J–DFLASH–06/06
CONTINUOUS ARRAY READ: By supplying an initial starting address for the main memory
array, the Continuous Array Read command can be utilized to sequentially read a continuous
stream of data from the device by simply providing a clock signal; no additional addressing
information or control signals need to be provided. The DataFlash incorporates an internal
address counter that will automatically increment on every clock cycle, allowing one continu-
ous read operation without the need of additional address sequences. To perform a
continuous read, an opcode of 68H or E8H must be clocked into the device followed by 24
address bits and 32 don’t care bits. The first six bits of the 24-bit address sequence are
reserved for upward and downward compatibility to larger and smaller density devices (see
Notes under “Command Sequence for Read/Write Operations” diagram). The next nine
address bits (PA8-PA0) specify which page of the main memory array to read, and the last
nine bits (BA8-BA0) of the 24-bit address sequence specify the starting byte address within
the page. The 32 don’t care bits that follow the 24 address bits are needed to initialize the read
operation. Following the 32 don’t care bits, additional clock pulses on the SCK pin will result in
serial data being output on the SO (serial output) pin.
The CS
pin must remain low during the loading of the opcode, the address bits, the don’t care
bits, and the reading of data. When the end of a page in main memory is reached during a
Continuous Array Read, the device will continue reading at the beginning of the next page with
no delays incurred during the page boundary crossover (the crossover from the end of one
page to the beginning of the next page). When the last bit in the main memory array has been
read, the device will continue reading back at the beginning of the first page of memory. As
with crossing over page boundaries, no delays will be incurred when wrapping around from
the end of the array to the beginning of the array.
A low-to-high transition on the CS
pin will terminate the read operation and tri-state the SO pin.
The maximum SCK frequency allowable for the Continuous Array Read is defined by the f
CAR
specification. The Continuous Array Read bypasses both data buffers and leaves the contents
of the buffers unchanged.
MAIN MEMORY PAGE READ: A main memory read allows the user to read data directly from
any one of the 512 pages in the main memory, bypassing the data buffer and leaving the con-
tents of the buffer unchanged. To start a page read, the 8-bit opcode, 52H or D2H, must be
clocked into the device followed by 24 address bits and 32 don’t care bits. In the
AT45DB011B, the first six address bits are reserved for larger density devices (see Notes on
page 15), the next nine address bits (PA8-PA0) specify the page address, and the next nine
address bits (BA8-BA0) specify the starting byte address within the page. The 32 don’t care
bits which follow the 24 address bits are sent to initialize the read operation. Following the 32
don’t care bits, additional pulses on SCK result in serial data being output on the SO (serial
output) pin. The CS
pin must remain low during the loading of the opcode, the address bits,
and the reading of data. When the end of a page in main memory is reached during a main
memory page read, the device will continue reading at the beginning of the same page. A low-
to-high transition on the CS
pin will terminate the read operation and tri-state the SO pin.
BUFFER READ: Data can be read from the data buffer using an opcode of 54H or D4H. To
perform a buffer read, the eight bits of the opcode must be followed by 15 don’t care bits, nine
address bits, and eight don’t care bits. Since the buffer size is 264 bytes, nine address bits
(BFA8- BFA0) are required to specify the first byte of data to be read from the buffer. The CS
pin must remain low during the loading of the opcode, the address bits, the don’t care bits, and
the reading of data. When the end of the buffer is reached, the device will continue reading
back at the beginning of the buffer. A low-to-high transition on the CS
pin will terminate the
read operation and tri-state the SO pin.
5
AT45DB011B
1984J–DFLASH–06/06
STATUS REGISTER READ: The status register can be used to determine the device’s
ready/busy status, the result of a Main Memory Page to Buffer Compare operation, or the
device density. To read the status register, an opcode of 57H or D7H must be loaded into the
device. After the last bit of the opcode is shifted in, the eight bits of the status register, starting
with the MSB (bit 7), will be shifted out on the SO pin during the next eight clock cycles. The
five most significant bits of the status register will contain device information, while the remain-
ing three least significant bits are reserved for future use and will have undefined values. After
bit 0 of the status register has been shifted out, the sequence will repeat itself (as long as CS
remains low and SCK is being toggled) starting again with bit 7. The data in the status register
is constantly updated, so each repeating sequence will output new data.
Ready/Busy status is indicated using bit 7 of the status register. If bit 7 is a 1, then the device
is not busy and is ready to accept the next command. If bit 7 is a 0, then the device is in a busy
state. The user can continuously poll bit 7 of the status register by stopping SCK at a low level
once bit 7 has been output. The status of bit 7 will continue to be output on the SO pin, and
once the device is no longer busy, the state of SO will change from 0 to 1. There are eight
operations which can cause the device to be in a busy state: Main Memory Page to Buffer
Transfer, Main Memory Page to Buffer Compare, Buffer to Main Memory Page Program with
Built-in Erase, Buffer to Main Memory Page Program without Built-in Erase, Page Erase,
Block Erase, Main Memory Page Program, and Auto Page Rewrite.
The result of the most recent Main Memory Page to Buffer Compare operation is indicated
using bit 6 of the status register. If bit 6 is a 0, then the data in the main memory page matches
the data in the buffer. If bit 6 is a 1, then at least one bit of the data in the main memory page
does not match the data in the buffer.
The device density is indicated using bits 5, 4, 3 and 2 of the status register. For the
AT45DB011B, the four bits are 0, 0, 1 and 1. The decimal value of these four binary bits does
not equate to the device density; the three bits represent a combinational code relating to dif-
fering densities of Serial DataFlash devices, allowing a total of sixteen different density
configurations.
Program and
Erase Commands
BUFFER WRITE: Data can be shifted in from the SI pin into the data buffer. To load data into
the buffer, an 8-bit opcode of 84H is followed by 15 don’t care bits and nine address bits
(BFA8-BFA0). The nine address bits specify the first byte in the buffer to be written. The data
is entered following the address bits. If the end of the data buffer is reached, the device will
wrap around back to the beginning of the buffer. Data will continue to be loaded into the buffer
until a low-to-high transition is detected on the CS
pin.
BUFFER TO MAIN MEMORY PAGE PROGRAM WITH BUILT-IN ERASE: Data written into
the buffer can be programmed into the main memory. An 8-bit opcode of 83H is followed by
the six reserved bits, nine address bits (PA8-PA0) that specify the page in the main memory
to be written, and nine additional don’t care bits. When a low-to-high transition occurs on the
CS
pin, the part will first erase the selected page in main memory to all 1s and then program
the data stored in the buffer into the specified page in the main memory. Both the erase and
the programming of the page are internally self-timed and should take place in a maximum
time of t
EP
. During this time, the status register will indicate that the part is busy.
Status Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RDY/BUSY
COMP0011XX
6
AT45DB011B
1984J–DFLASH–06/06
BUFFER TO MAIN MEMORY PAGE PROGRAM WITHOUT BUILT-IN ERASE: A previously
erased page within main memory can be programmed with the contents of the buffer. An 8-bit
opcode of 88H is followed by the six reserved bits, nine address bits (PA8-PA0) that specify
the page in the main memory to be written, and nine additional don’t care bits. When a low-to-
high transition occurs on the CS
pin, the part will program the data stored in the buffer into the
specified page in the main memory. It is necessary that the page in main memory that is being
programmed has been previously erased. The programming of the page is internally self-
timed and should take place in a maximum time of t
P
. During this time, the status register will
indicate that the part is busy.
Successive page programming operations without doing a page erase are not recommended.
In other words, changing bytes within a page from a “1” to a “0” during multiple page program-
ming operations without erasing that page is not recommended.
PAGE ERASE: The optional Page Erase command can be used to individually erase any
page in the main memory array allowing the Buffer to Main Memory Page Program without
Built-in Erase command to be utilized at a later time. To perform a Page Erase, an opcode of
81H must be loaded into the device, followed by six reserved bits, nine address bits (PA8-
PA0), and nine don’t care bits. The nine address bits are used to specify which page of the
memory array is to be erased. When a low-to-high transition occurs on the CS
pin, the part will
erase the selected page to 1s. The erase operation is internally self-timed and should take
place in a maximum time of t
PE
. During this time, the status register will indicate that the part is
busy.
BLOCK ERASE: A block of eight pages can be erased at one time allowing the Buffer to Main
Memory Page Program without Built-in Erase command to be utilized to reduce programming
times when writing large amounts of data to the device. To perform a Block Erase, an opcode
of 50H must be loaded into the device, followed by six reserved bits, six address bits (PA8-
PA3), and 12 don’t care bits. The six address bits are used to specify which block of eight
pages is to be erased. When a low-to-high transition occurs on the CS
pin, the part will erase
the selected block of eight pages to 1s. The erase operation is internally self-timed and should
take place in a maximum time of t
BE
. During this time, the status register will indicate that the
part is busy.
Block Erase Addressing
PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Block
000000XXX0
000001XXX1
000010XXX2
000011XXX3
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111100XXX60
111101XXX61
111110XXX62
111111XXX63
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32

AT45DB011B-CC

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IC FLASH 1M SPI 20MHZ 9CBGA
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