830584AGILFT Datasheet 830584AGILFT, 830584AGILF | P4-P6

830584I Datasheet

Symbol Parameter Test Conditions Minimum Typical

†

Maximum Units

clk

Clock Frequency; NOTE 1 0 140 MHz

Propagation Delay, Low to High;

NOTE 2

1.8 2.5 3 ns

Propagation Delay, High to Low;

NOTE 2

1.8 2.4 3 ns

tsk(o) Output Skew; NOTE 3, 4 50 100 ps

tsk(p) Pulse Skew 140MHz 170 ps

tsk(pr) Process Skew 200 300 ps

tsk(pp) Part-to-Part Skew; NOTE 4, 5 250 400 ps

tjit

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter section

140MHz, Integration Range:

10kHz – 20MHz

0.15 ps

high

CLK High Time

66MHz 6 ns

140MHz 3 ns

low

CLK Low Time

66MHz 6 ns

140MHz 3 ns

Output Rise Slew Rate

‡

0.2V

to 0.6V

1.5 2.7 4 V/ns

Output Fall Slew Rate

‡

0.6V

to 0.2V

1.5 2.7 4 V/ns

†

All typical values are at respective nominal V

‡

This symbol is according to PCI-X terminology.

NOTE 1: Switching characteristics over recommended ranges of supply voltages and operating free-air temperature,

= 10pF, V

= 3.3V ± 0.3V.

NOTE 2: Measured from V

/2 of the input to V

/2 of the output.

NOTE 3: Deﬁ ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at V

/2.

NOTE 4: This parameter is deﬁ ned in accordance with JEDEC Standard 65.

NOTE 5: Deﬁ ned as skew between outputs on different devices operating a the same supply voltages and

with equal load conditions. Using the same type of input on each device, the output is measured at V

/2.

TABLE 5. AC CHARACTERISTICS, V

= 3.3V ± 0.3V, TA = -40°C TO 85°C

830584I Datasheet

ADDITIVE PHASE JITTER

The spectral purity in a band at a speciﬁ c offset from the fundamental

compared to the power of the fundamental is called the dBc Phase

Noise. This value is normally expressed using a Phase noise plot

and is most often the speciﬁ ed plot in many applications. Phase

noise is deﬁ ned as the ratio of the noise power present in a 1Hz

band at a speciﬁ ed offset from the fundamental frequency to the

power value of the fundamental. This ratio is expressed in decibels

As with most timing speciﬁ cations, phase noise measurements has

issues relating to the limitations of the equipment. Often the noise

ﬂ oor of the equipment is higher than the noise ﬂ oor of the device.

(dBm) or a ratio of the power in the 1Hz band to the power in the

fundamental. When the required offset is speciﬁ ed, the phase noise

is called a dBc value, which simply means dBm at a speciﬁ ed offset

from the fundamental. By investigating jitter in the frequency domain,

we get a better understanding of its effects on the desired application

over the entire time record of the signal. It is mathematically possible

to calculate an expected bit error rate given a phase noise plot.

This is illustrated above. The device meets the noise ﬂ oor of what

is shown, but can actually be lower. The phase noise is dependent

on the input source and measurement equipment.

OFFSET FROM CARRIER FREQUENCY (HZ)

SSB PHASE NOISE dBc/HZ

Input/Output Additive Phase Jitter at

140MHz (12kHz – 20MHz) = 0.15ps typical

830584I Datasheet

PARAMETER MEASUREMENT INFORMATION

PART-TO-PART SKEW

OUTPUT SKEW3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT

PROPAGATION DELAY

OUTPUT RISE/FALL SLEW RATES CLOCK WAVEFORM

OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

P1-P3 P4-P6 P7-P9 P10-P12

830584AGILFT

Mfr. #:

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Manufacturer:

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Description:

Clock Buffer LVCMOS 4 OUT FANOUT

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830584AGILFT

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