TJA1043 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 6 — 10 November 2017 10 of 32
NXP Semiconductors
TJA1043
High-speed CAN transceiver
timers. Once set, the Wake flag status is immediately available on pins ERR_N and RXD
(provided V
IO
and V
BAT
are present). This flag is also set at power-on and cleared when
the UV
NOM
flag is set or the transceiver enters Normal mode.
7.2.5 Remote wake-up (via the CAN bus)
The TJA1043 wakes up from Standby or Sleep mode when a dedicated wake-up pattern
(specified in ISO 11898-2: 2016) is detected on the bus. This filtering helps avoid spurious
wake-up events. A spurious wake-up sequence could be triggered by, for example, a
dominant clamped bus or by dominant phases due to noise or spikes on the bus.
The wake-up pattern consists of:
a dominant phase of at least t
wake(busdom)
followed by
a recessive phase of at least t
wake(busrec)
followed by
a dominant phase of at least t
wake(busdom)
Dominant or recessive bits between the above mentioned phases that are shorter than
t
wake(busdom)
and t
wake(busrec)
respectively are ignored.
The complete dominant-recessive-dominant pattern must be received within t
to(wake)bus
to
be recognized as a valid wake-up pattern (see Figure 5
). Otherwise, the internal wake-up
logic is reset. The complete wake-up pattern will then need to be retransmitted to trigger a
wake-up event. Pin RXD remains HIGH until the wake-up event has been triggered.
A wake-up event is not flagged on RXD if any of the following events occurs while a valid
wake-up pattern is being received:
The TJA1043 switches to Normal mode
The complete wake-up pattern was not received within t
to(wake)bus
A V
CC
or V
IO
undervoltage is detected (UV
NOM
flag set; see Section 7.2.1)
7.2.6 Wake-up source flag
Wake-up source recognition is provided via the Wake-up source flag, which is set when
the Wake flag is set by a local wake-up request via the WAKE pin. The Wake-up source
flag can be polled via the ERR_N pin in Normal mode (see Table 5
). This flag is also set at
power-on and cleared when the transceiver leaves Normal mode.
Fig 5. Wake-up timing
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TJA1043 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 6 — 10 November 2017 11 of 32
NXP Semiconductors
TJA1043
High-speed CAN transceiver
7.2.7 Bus failure flag
The Bus failure flag is set if the transceiver detects a bus line short-circuit condition to
V
BAT
, V
CC
or GND during four consecutive dominant-recessive cycles on pin TXD, while
trying to drive the bus lines dominant. The Bus failure flag can be polled via the ERR_N
pin in Normal mode (see Table 5
). This flag is cleared at power-on or when the transceiver
re-enters Normal mode.
7.2.8 Local failure flag
In Normal and Listen-only modes, the transceiver can distinguish four different local
failure events, any of which will cause the Local failure flag to be set. The four local failure
events are: TXD dominant clamping, TXD-to-RXD short circuit, bus dominant clamping
and an overtemperature event. The nature and detection of these local failures is
described in Section 7.3
. The Local failure flag can be polled via the ERR_N pin in
Listen-only mode (see Table 5
). This flag is cleared at power-on, when entering Normal
mode or when RXD is dominant while TXD is recessive, provided that all local failures
have been resolved.
7.3 Local failures
The TJA1043 can detect four different local failure conditions. Any of these failures will set
the Local failure flag, and in most cases the transmitter of the transceiver will be disabled.
7.3.1 TXD dominant time-out function
A permanent LOW level on pin TXD (due to a hardware or software application failure)
would drive the CAN bus into a permanent dominant state, blocking all network
communications. The TXD dominant time-out function prevents such a network lock-up by
disabling the transmitter if pin TXD remains LOW for longer than the TXD dominant
time-out time t
to(dom)TXD
. The t
to(dom)TXD
timer defines the minimum possible bit rate of
40 kbit/s. The transmitter remains disabled until the Local failure flag has been cleared.
7.3.2 TXD-to-RXD short-circuit detection
A short-circuit between pins RXD and TXD would lock the bus in a permanent dominant
state once it had been driven dominant, because the low-side driver of RXD is typically
stronger than the high-side driver of the controller connected to TXD. TXD-to-RXD
short-circuit detection prevents such a network lock-up by disabling the transmitter. The
transmitter remains disabled until the Local failure flag has been cleared.
7.3.3 Bus dominant time-out function
A CAN bus short circuit (to V
BAT
, V
CC
or GND) or a failure in one of the other network
nodes could result in a differential voltage on the bus high enough to represent a bus
dominant state. Because a node will not start transmission if the bus is dominant, the
normal bus failure detection will not detect this failure, but the bus dominant clamping
detection will. The Local failure flag is set if the dominant state on the bus persists for
longer than t
to(dom)bus
. By checking this flag, the controller can determine if a clamped bus
is blocking network communications. There is no need to disable the transmitter. Note that
the Local failure flag does not retain a bus dominant clamping failure, and is released as
soon as the bus returns to recessive state.
TJA1043 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 6 — 10 November 2017 12 of 32
NXP Semiconductors
TJA1043
High-speed CAN transceiver
7.3.4 Overtemperature detection
If the junction temperature becomes excessive, the transmitter will shut down in time to
protect the output drivers from overheating without compromising the maximum operating
temperature. The transmitter will remain disabled until the Local failure flag has been
cleared.
7.4 SPLIT pin
Using the SPLIT pin on the TJA1043 in conjunction with a split termination network (see
Figure 6
and Figure 9) can help to stabilize the recessive voltage level on the bus. This
will reduce EME in networks with DC leakage to ground (e.g. from deactivated nodes with
poor bus leakage performance). In Normal and Listen-only modes, pin SPLIT delivers a
DC output voltage of 0.5V
CC
. In Standby, Go-to-Sleep and Sleep modes, pin SPLIT is
floating.
7.5 V
IO
supply pin
Pin V
IO
should be connected to the microcontroller supply voltage (see Figure 9). This will
cause the signal levels of pins TXD, RXD, STB_N, EN and ERR_N to be adjusted to the
I/O levels of the microcontroller, facilitating direct interfacing without the need for glue
logic.
7.6 WAKE pin
A local wake-up event is triggered by a LOW-to-HIGH or HIGH-to-LOW transition on the
WAKE pin, allowing for maximum flexibility when designing a local wake-up circuit.To
minimize current consumption, the internal bias voltage will follow the logic state on the
pin after a delay of t
wake
. A HIGH level on pin WAKE is followed by an internal pull-up to
V
BAT
. A LOW level on pin WAKE is followed by an internal pull-down towards GND. In
applications that don’t make use of the local wake-up facility, it is recommended that the
WAKE pin be connected to V
BAT
or GND to ensure optimal EMI performance.
Fig 6. Stabilization circuit and application
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TJA1043TKJ

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
CAN Interface IC TJA1043TK/HVSON14/REEL13
Lifecycle:
New from this manufacturer.
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