Workaround:
No workaround.
Fix plan:
Fixed in datecodes XX0324 and later.
SECF003: BDM Load of SR Does Not Enable Stack Pointer Exchange
Errata type:
Silicon
Affects:
BDM
Description:
The V2 core used in this device adds support for separate user and supervisor stack pointers.
The hardware implements an active stack pointer and an other_stack_pointer. Whenever the
operating mode of the processor changes (supervisor to user or user to supervisor), the
processor hardware exchanges the active SP and the other SP.
This exchange operation does not work when the processor mode is changed by a write to the
SR from the BDM port. The hardware in the processor core required to process the BDM
load_SR operation and enable the stack pointer exchange is missing.
The exchange works properly when the SR is changed through software.
Workaround:
Use software for any operations that require exchanging the stack pointers.
Fix plan:
Currently, there are no plans to fix this.
SECF002: Unexpected Pipeline Stall on EMAC Load/Store Accumulator Instruction
Errata type:
Silicon
Affects:
EMAC
Description:
An unexpected pipeline stall occurs for accumulator load and accumulator store instructions
that immediately follow a load accumulator or MAC instruction.
Specifically, the operand execution pipeline (OEP) experiences a 2T pipeline stall when a load/
store accumulator instruction enters the pipeline immediately after any load accumulator or
MAC instruction. The pipeline is supposed to stall only if there is a store accumulator
instruction immediately following a load or MAC instruction that updated the specified
accumulator.
A simple example can be created to expose this problem:
mac.l ra,rb,acc0
mac.l rc,rd,acc0
mov.l acc1,rx
In the above example, the store of
acc1 (mov.l acc1,rx)
should not experience any stall because that accumulator is not being updated. In the current
V2 + EMAC implementation, it incorrectly stalls for two cycles.
NOTE
The operation of the instructions is correct. The problem is that the
expected timing is not met.
Workaround:
No workaround.
Fix plan:
Fixed in datecodes XXX0327 and later.
MCF5216 Chip Errata, Rev 8, 02/2015
Freescale Semiconductor, Inc. 3