Workaround:
Workaround Step 1 (Always do this): Use FLASHBAR[6] to disable the address speculation
mechanisms of the flash controller. The default configuration (FLASHBAR[6] = 0) enables the
address speculation. If FLASHBAR[6] equals 1, address speculation is disabled. Core
performance may be degraded from 4% – 9%, depending heavily on application code.
NOTE
FLASHBAR[6] is user accessible via the movec instruction.
FLASHBAR[6] always reads back as 0.
NOTE
On MCF528x and MCF521x devices FLASHBAR[6] is already set
to 1 for datecodes XXX0327 and later. The bit still reads back as 0.
Workaround Step 2a (Select one of the step 2 options to use): Construct the device
memory map so the flash and SRAM spaces are disjoint within the modulo-(flash_size)
addresses. In some cases if this approach is selected, the upper portion of the flash memory
might be unused and the SRAM be mapped to this unused flash space.
Consider an example where the flash memory size is 256 Kbytes and the on-chip SRAM size
is 32 Kbytes. If 224 Kbytes or less of flash are used, the SRAM can be based at the upper 32
Kbytes (within the modulo-256 Kbyte address) of the flash address space:
Flash: size = 0x40000, base = 0x0000_0000
RAM: size = 0x08000, base = 0x8003_8000 = RAM_BASE+(256-32) Kbytes
where the flash and SRAM base addresses are unique BA[31:16].
In summary, this approach can be applied if the combined size of the used flash and used
SRAM is less than the total flash size, with the flash contents justified to the lower address
range and the SRAM contents justified to the upper address range.
Workaround Step 2b (Select one of the step 2 options to use): Separate the contents of
the SRAM and the flash memory into exclusive categories and use the address space mask
bits in FLASHBAR and RAMBAR to restrict accesses. For example, if the flash contains only
instructions and the SRAM contains only operands (all data), the appropriate address space
mask fields are specified to prevent flash and SRAM accesses from overlapping.
Workaround Step 3a (Select one of the step 3 options to use if external parallel memory
is used in the system): Do not enable caching of external memories. With caching disabled
the timing requirements for an issue to occur will not be met, so this will prevent conflicts
between flash and external parallel memory accesses through the EIM or SDRAMC.
Workaround Step 3b (Select one of the step 3 options to use if external parallel memory
is used in the system): Separate the contents of the EIM and/or SDRAM and the flash
memory into exclusive categories and use the address space mask bits in FLASHBAR,
CSMRn, and DMRn to restrict accesses. For example, if the flash contains only instructions
and the SDRAM contains only operands (all data), the appropriate address space mask fields
are specified to prevent flash and SRAM accesses from overlapping.
MCF5216 Chip Errata, Rev 8, 02/2015
Freescale Semiconductor, Inc. 9