CPC7593ZA Datasheet CPC7593BA, CPC7593BBTR, CPC7593BC | P19-P21

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2.3.8 Alternate Break-Before-Make Operation Logic Table (Ringing to Talk Transition)

2.4 Data Latch

The CPC7593 has an integrated transparent data

latch. The latch enable operation is controlled by TTL

logic input levels at the LATCH pin. Data input to the

latch are via the input pins, while the output of the data

latch are internal nodes used for state control. When

the LATCH enable control pin is at logic 0 the data

latch is transparent and the input data control signals

flow directly through the latch to the state control

circuitry. A change in input will be reflected by a

change in switch state. Whenever the LATCH enable

control pin is at logic 1, the latch is active and data is

locked. Subsequent input changes will not result in a

change to the control logic or affect the existing switch

state.

Switches will remain in the state they were in when the

LATCH pin changes from logic 0 to logic 1 and will not

respond to changes in input as long as the latch is at

logic 1. However, neither the T

input nor the T

output control functions are affected by the latch

function. Internal thermal shutdown control and

external “All-off” control via T

is not affected by the

state of the LATCH enable input.

2.5 T

Pin Description

The T

pin is a bi-directional I/O structure with an

internal pull up sourced from V

. As an output, this

pin indicates the status of the thermal shutdown

circuitry. Typically, during normal operation, this pin will

be pulled up to V

but under fault conditions that

create excess thermal loading the CPC7593 will enter

thermal shutdown and a logic low will be output.

As an input, the T

pin can be utilized to place the

CPC7593 into the “All-Off” state by simply pulling the

input low via an open-collector type buffer. Using a

standard output with an active logic high drive

capability will sink the pull-up current resulting in

unnecessary power consumption.

Use of a standard output buffer with an active high

drive capability will not disable the thermal shutdown

mechanism. The ability to enter thermal shutdown

during a fault condition is independent of the

connection at the T

input.

The CPC7593’s internal pull up has a nominal value of

16A.

2.6 Ringing Switch Zero-Cross Current Turn Off

After the application of a logic input to turn SW4 off,

the ringing switch is designed to delay the change in

state until the next zero-crossing. Once on, the switch

requires a zero-current cross to turn off, and therefore

should not be used to switch a pure DC signal. The

switch will remain in the on state no matter the logic

input until the next zero crossing. These switching

characteristics will reduce and possibly eliminate

overall system impulse noise normally associated with

ringing switches. See application note AN-144, Impulse

Noise Benefits of Line Card Access Switches for more

information. The attributes of ringing switch SW4 may

make it possible to eliminate the need for a zero-cross

switching scheme. A minimum impedance of 300 in

series with the ringing generator is recommended.

State

RINGING

TESTin

TESTout

Latch

Timing

Break

Switches

Ringing

Return

Switch

(SW3)

Ringing

Switch

(SW4)

Test

Switches

Ringing 1 0 0 0 Z - Off

On On Off

All-off 1 0 1

Hold this state for at least

one-half of ringing cycle.

SW4 waiting for zero current

to turn off.

Off Off

On Off

Break-

Before-

Make

000

Zero current has occurred.

SW4 has opened

Off Off Off Off

Talk 0 0 0 0 Z Break switches close.

On Off Off Off

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CPC7593

2.7 Power Supplies

Both a +5 V supply and battery voltage are connected

to the CPC7593. Switch state control is powered

exclusively by the +5 V supply. As a result, the

CPC7593 exhibits extremely low power consumption

during active and idle states.

Although battery power is not used for switch control, it

is required to supply trigger current for the integrated

internal protection circuitry SCR during fault

conditions. This integrated SCR is designed to

activate whenever the voltage at T

BAT

or R

BAT

drops 2

to 4 V below the applied voltage on the V

BAT

pin.

Because the battery supply at this pin is required to

source trigger current during negative overvoltage

fault conditions at tip and ring, it is important that the

net supplying this current be a low impedance path for

high speed transients such as lightning. This will

permit trigger currents to flow enabling the SCR to

activate and thereby prevent a fault induced negative

overvoltage event at the T

BAT

or R

BAT

nodes.

2.8 Battery Voltage Monitor

The CPC7593 also uses the V

BAT

pin to monitor

battery voltage. If the system battery voltage is lost,

the CPC7593 immediately enters the all-off state. It

remains in this state until the system battery voltage is

restored. The device also enters the all-off state if the

battery voltage rises more positive than about –10 V

and remains in the all-off state until the battery voltage

drops below –15 V. This battery monitor feature draws

a small current from the battery (less than 1 A

typical) and will add slightly to the device’s overall

power dissipation.

This monitor function performs properly if the

CPC7593 and SLIC share a common battery supply

origin. Otherwise, if battery is lost to the CPC7593 but

not to the SLIC, then the V

BAT

pin will be internally

biased by the potential applied at the T

BAT

or R

BAT

pins via the internal protection circuitry SCR trigger

current path.

2.9 Protection

2.9.1 Diode Bridge/SCR

The CPC7593 uses a combination of current limited

break switches, a diode bridge/SCR clamping circuit,

and a thermal shutdown mechanism to protect the

SLIC device or other associated circuitry from damage

during line transient events such as lightning. During a

positive transient condition, the fault current is

conducted through the diode bridge to ground via

GND

. Voltage is clamped to a diode drop above

ground. During a negative transient of 2-4 volts more

negative than the voltage source at V

BAT

, the SCR

conducts and faults are shunted to F

GND

via the SCR

or the diode bridge.

In order for the SCR to crowbar or foldback, the SCR’s

on-voltage (see “Protection Circuitry Electrical

Specifications” on page 13) must be less than the

applied voltage at the V

BAT

pin. If the V

BAT

voltage is

less negative than the SCR on-voltage, or if the V

BAT

supply is unable to source the trigger current, the SCR

will not crowbar.

For power induction or power-cross fault conditions,

the positive cycle of the transient is clamped to a diode

drop above ground and the fault current is directed to

ground. The negative cycle of the transient will cause

the SCR to conduct when the voltage exceeds the

BAT

reference voltage by two to four volts, steering

the fault current to ground.

Note: Neither the CPC7593xB or the CPC7593xD

contains the protection SCR but instead uses a diode

bridge to clamp both polarities of a fault transient.

These diodes direct the negative potential’s fault

current to the V

BAT

pin.

2.9.2 Current Limiting function

If a lightning strike transient occurs when the device is

in the talk state, the current is passed along the line to

the integrated protection circuitry and restricted by the

dynamic current limit response of the active switches.

During the talk state when a 1000V 10x1000 S pulse

(GR-1089-CORE lightning) is applied to the line

though a properly clamped external protector, the

current seen at T

LINE

or R

LINE

will be a pulse with a

typical magnitude of 2.5 A and a duration of less than

0.5 s.

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If a power-cross fault occurs with the device in the talk

state, the current is passed though the break switches

SW1 and SW2 on to the integrated protection circuit

but is limited by the dynamic DC current limit response

of the two break switches. The DC current limit

specified over temperature is between 80mA and

425mA, and the circuitry has a negative temperature

coefficient. As a result, if the device is subjected to

extended heating due to a power cross fault condition,

the measured current into T

LINE

or R

LINE

will decrease

as the device temperature increases. If the device

temperature rises sufficiently, the temperature

shutdown mechanism will activate and the device will

enter the all-off state.

2.10 Thermal Shutdown

The thermal shutdown mechanism will activate when

the device die temperature reaches a minimum of

110° C, placing the device in the all-off state

regardless of IN

RINGING

, IN

TESTin

and IN

TESTout

logic

inputs. During thermal shutdown events the T

will output a logic low with a nominal 0 V level. A logic

high is output from the T

pin during normal

operation with a typical output level equal to V

If presented with a short duration transient such as a

lightning event, the thermal shutdown feature will

typically not activate. But in an extended power-cross

event, the device temperature will rise and the thermal

shutdown mechanism will activate forcing the switches

to the all-off state. At this point the current measured

into T

LINE

or R

LINE

will drop to zero. Once the device

enters thermal shutdown it will remain in the all-off

state until the temperature of the die drops below the

deactivation level of the thermal shutdown circuit. This

permits the device to return to normal operation. If the

transient has not passed, current will again flow up to

the value allowed by the dynamic DC current limiting

of the switches and heating will resume, reactivating

the thermal shutdown mechanism. This cycle of

entering and exiting the thermal shutdown mode will

continue as long as the fault condition persists. If the

magnitude of the fault condition is great enough, the

external secondary protector will activate shunting the

fault current to ground.

The thermal shutdown mechanism of the CPC7593

cannot be disabled by forcing a logic 1 to T

Therefore, only an open-collector or open-drain type

interface should be used to control the T

pin’s input

function.

2.11 External Protection Elements

The CPC7593 requires only over voltage secondary

protection on the loop side of the device. The

integrated protection feature described above negates

the need for additional external protection on the SLIC

side. The secondary protector must limit voltage

transients to levels that do not exceed the breakdown

voltage or input-output isolation barrier of the

CPC7593. A foldback or crowbar type protector is

recommended to minimize stresses on the CPC7593.

Consult IXYS Integrated Circuits Division’s application

note, AN-100, “Designing Surge and Power Fault

Protection Circuits for Solid State Subscriber Line

Interfaces” for equations related to the specifications of

external secondary protectors, fused resistors and

PTCs.

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CPC7593ZA

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