ADF4360-3 Data Sheet
Rev. E | Page 10 of 24
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4360-3 allows the user to
access various internal points on the chip. The state of MUX-
OUT is controlled by M3, M2, and M1 in the function latch.
The full truth table is shown on Table 7. Figure 13 shows the
MUXOUT section in block diagram form.
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital and analog. Digital lock detect is active high. When LDP
in the R counter latch is set to 0, digital lock detect is set high
when the phase error on three consecutive phase detector cycles
is less than 15 ns.
With LDP set to 1, five consecutive cycles of less than 15 ns
phase error are required to set the lock detect. It stays set high
until a phase error of greater than 25 ns is detected on any sub-
sequent PD cycle.
The N-channel open-drain analog lock detect should be operat-
ed with an external pull-up resistor of 10 kΩ nominal. When
lock has been detected, this output is high with narrow low-
going pulses.
R COUNTER OUTPUT
N COUNTER OUTPUT
DIGITAL LOCK DETECT
DGND
CONTROLMUX
MUXOUT
DV
DD
ANALOG LOCK DETECT
SDOUT
04437-013
Figure 13. MUXOUT Circuit
INPUT SHIFT REGISTER
The digital section of the ADF4360-3 includes a 24-bit input
shift register, a 14-bit R counter, and an 18-bit N counter,
comprised of a 5-bit A counter and a 13-bit B counter. Data is
clocked into the 24-bit shift register on each rising edge of CLK.
The data is clocked in MSB first. Data is transferred from the
shift register to one of four latches on the rising edge of LE. The
destination latch is determined by the state of the two control
bits (C2, C1) in the shift register. These are the two LSBs—DB1,
DB0—as shown in Figure 2.
The truth table for these bits is shown in Table 5. Tabl e 6 shows
a summary of how the latches are programmed. Note that the
test mode latch is used for factory testing and should not be
programmed by the user.
Table 5. C2 and C1 Truth Table
Control Bits
Data Latch
C2 C1
0 0 Control Latch
0 1 R Counter
1 0 N Counter (A and B)
1 1 Test Mode Latch
VCO
The VCO core in the ADF4360-3 uses eight overlapping bands,
as shown in Figure 14, to allow a wide frequency range to be
covered without a large VCO sensitivity (K
V
) and resultant poor
phase noise and spurious performance.
The correct band is chosen automatically by the band select
logic at power-up or whenever the N counter latch is updated. It
is important that the correct write sequence be followed at pow-
er-up. This sequence is
1. R counter latch
2. Control latch
3. N counter latch
During band select logic, which takes five PFD cycles, the VCO
V
TUNE
is disconnected from the output of the loop filter and
connected to an internal reference voltage.
04437-014
0.7
0.5
0.9
1.1
1.3
1.5
1.7
1.9
2.1
2.7
2.5
2.3
2.9
3.1
3.3
20501950185017501650155014501350
FREQUENCY (MHz)
VOLTAGE (V)
Figure 14. Frequency vs. V
TUNE
, ADF4360-3
The R counter output is used as the clock for the band select logic
and should not exceed 1 MHz. A programmable divider is provid-
ed at the R counter input to allow division by 1, 2, 4, or 8 and is
controlled by Bits BSC1 and BSC2 in the R counter latch. Where
the required PFD frequency exceeds 1 MHz, the divide ratio should
be set to allow enough time for correct band selection.
After band select, normal PLL action resumes. The nominal value
of K
V
is 45 MHz/V or 23 MHz/V if divide-by-2 operation has been
selected (by programming DIV2 [DB22] high in the N counter
latch). The ADF4360-3 contains linearization circuitry to mini-
mize any variation of the product of I
CP
and K
V
.