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ADF4360-3BCPZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
Data Sheet ADF4360-3
Rev. E | Page 15 of 24
Table 9. R Counter Latch
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11
DB10 DB9 DB8 DB7 DB6
DB5 DB4 DB3 DB2 DB1 DB0
C2 (0) C1 (1)
R1R2R3R4R5R7R8R9R10R11R12R13R14ABP1ABP2LDPTMBBSC1 R6
CONTROL
BITS
BAND
SELECT
CLOCK
ANTI-
BACKLASH
PULSE
WIDTH
14-BIT REFERENCE COUNTER
DB21DB22DB23
LOCK
DETECT
PRECISION
TEST
MODE
BIT
RESERVED
RESERVED
BSC2RSVRSV
TEST MODE
BIT SHOULD
BE SET TO 0
FOR NORMAL
OPERATION.
R14 R13 R12 R3 R2 R1 DIVIDE RATIO
.......... 00 0 0
0 0 0
0 0 0
0 0 0
0 0 1
.......... 0 1 1 2
.......... 0 1 0 3
.......... 1 0 1 4
.......... .. . .
. . .
. . .
. . .
.......... . . . .
.......... . . . .
.......... 11 1 1
1 1 1
1 1 1
1 1 1
0 0 16380
.......... 1 0 1 16381
.......... 1 1 0 16382
.......... 1 1 1 16383
THESE BITS ARE NOT
USED BY THE DEVICE
AND ARE DON'T CARE
BITS.
04437-019
LDP LOCK DETECT PRECISION
0 THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
1 FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
ABP2 ABP1 ANTIBACKLASH PULSE WIDTH
0 0 3.0ns
0 1 1.3ns
1 0 6.0ns
1 1 3.0ns
BSC2 BSC1 BAND SELECT CLOCK DIVIDER
0 0 1
0 1 2
1 0 4
1 1 8
ADF4360-3 Data Sheet
Rev. E | Page 16 of 24
POWER-UP
Power-Up Sequence
The correct programming sequence for the ADF4360-3 after
power-up is:
1. R counter latch
2. Control latch
3. N counter latch
Initial Power-Up
Initial power-up refers to programming the device after the
application of voltage to the AV
DD
, DV
DD
, V
VCO
, and CE pins. On
initial power-up, an interval is required between programming
the control latch and programming the N counter latch.
This interval is necessary to allow the transient behavior of the
ADF4360-3 during initial power-up to have settled. During
initial power-up, a write to the control latch powers up the de-
vice, and the bias currents of the VCO begins to settle. If these
currents have not settled to within 10% of their steady-state
value, and if the N counter latch is then programmed, the VCO
may not be able to oscillate at the desired frequency, which does
not allow the band select logic to choose the correct frequency
band, and the ADF4360-3 may not achieve lock. If the recom-
mended interval is inserted, and the N counter latch is pro-
grammed, the band select logic can choose the correct frequen-
cy band, and the device locks to the correct frequency.
The duration of this interval is affected by the value of the ca-
pacitor on the C
N
pin (Pin 14). This capacitor is used to reduce
the close-in noise of the ADF4360-3 VCO. The recommended
value of this capacitor is 10 µF. Using this value requires an in-
terval of ≥5 ms between the latching in of the control latch bits
and latching in of the N counter latch bits. If a shorter delay is
required, this capacitor can be reduced. A slight phase noise
penalty is incurred by this change, which is explained further
in Tabl e 10.
Table 10. C
N
Capacitance vs. Interval and Phase Noise
C
N
Value Recommended Interval Between Control Latch and N Counter latch Open-Loop Phase Noise at 10 kHz Offset
10 µF ≥5 ms −87 dBc
440 nF ≥600 µs −86 dBc
CLOCK
POWER-UP
DATA
LE
R COUNTER
LATCH DATA
CONTROL
LATCH DATA
N COUNTER
LATCH DATA
REQUIRED INTERVAL
CONTROL LATCH WRITE TO
N COUNTER LATCH WRITE
04437-020
Figure 16. ADF4360-3 Power-Up Timing
Data Sheet ADF4360-3
Rev. E | Page 17 of 24
Hardware Power-Up/Power-Down
If the device is powered down via the hardware (using the CE
pin) and powered up again without any change to the N counter
register during power-down, the device locks at the correct
frequency because the device is already in the correct frequency
band. The lock time depends on the value of capacitance on the
C
N
pin, which is <5 ms for 10 µF capacitance. The smaller ca-
pacitance of 440 nF on this pin enables lock times of <600 µs.
The N counter value cannot be changed while the device is in
power-down, since the device may not lock to the correct fre-
quency on power-up. If it is updated, the correct programming
sequence for the device after power-up is to the R counter latch,
followed by the control latch, and finally the N counter latch,
with the required interval between the control latch and N
counter latch, as described in the Initial Power-Up section.
Software Power-Up/Power-Down
If the device is powered down via the software (using the con-
trol latch) and powered up again without any change to the N
counter latch during power-down, the device locks at the cor-
rect frequency because the device is already in the correct fre-
quency band. The lock time depends on the value of capaci-
tance on the C
N
pin, which is <5 ms for 10 µF capacitance. The
smaller capacitance of 440 nF on this pin enables lock times of
<600 µs.
The N counter value cannot be changed while the device is in
power-down because the device may not lock to the correct
frequency on power-up. If it is updated, the correct program-
ming sequence for the devices after power-up is to the R coun-
ter latch, followed by the control latch, and finally the N counter
latch, with the required interval between the control latch and
N counter latch, as described in the Initial Power-Up section.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

ADF4360-3BCPZ

Mfr. #:
Buy ADF4360-3BCPZ
Manufacturer:
Analog Devices Inc.
Description:
Phase Locked Loops - PLL Intg Integer-N VCO Out Freq 1600-1950
Lifecycle:
New from this manufacturer.
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