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74ALVCH16601DGGS

P1-P3P4-P6P7-P9P10-P12P13-P13
Philips Semiconductors Product specification
74ALVCH1660118-bit universal bus transceiver (3-State)
1998 Sep 24
3
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
27
28
30
29
OE
AB
LE
AB
A0
GND
A1
A2
A3
A4
A5
GND
A6
A7
A8
A9
A11
GND
A12
V
CC
A10
A13
A14
A15
A16
A17
V
CC
GND
OE
BA
LE
BA
CE
AB
CP
AB
B0
GND
B1
B2
B3
B4
B5
GND
B6
B7
B8
B9
B11
GND
B12
V
CC
B10
B13
B14
B15
B16
B17
V
CC
GND
CP
BA
CE
BA
SW00129
LOGIC SYMBOL
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
OE
AB
LE
AB
CP
AB
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
OE
BA
LE
BA
CP
BA
3
5
6
8
10
12
13
14
15
16
17
19
20
21
23
24
26
1
2
55
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
27
28
30
9
SW00130
CE
AB
56
CE
BA
29
PIN DESCRIPTION
PIN NUMBER SYMBOL NAME AND FUNCTION
1 OE
AB
Output enable A-to-B
2 LE
AB
Latch enable A-to-B
3, 5, 6, 8, 9,
10, 12, 13, 14,
15, 16, 17, 19,
20, 21, 23, 24,
26
A0 to A17 Data inputs/outputs
4, 11, 18, 25,
32, 39, 46, 53
GND Ground (0V)
7, 22, 35, 50 V
CC
Positive supply voltage
27 OE
BA
Output enable B-to-A
28 LE
BA
Latch enable B-to-A
29 CE
BA
Clock enable B-to-A
30 CP
BA
Clock input B-to-A
54, 52, 51, 49,
48, 47, 45, 44,
43, 42, 41, 40,
38, 37, 36, 34,
33, 31
B0 to B17 Data inputs/outputs
55 CP
AB
Clock input A-to-B
56 CE
AB
Clock enable A-to-B
Philips Semiconductors Product specification
74ALVCH1660118-bit universal bus transceiver (3-State)
1998 Sep 24
4
LOGIC DIAGRAM (one section)
CE
C1
CP
1D
CE
C1
CP
1D
18 IDENTICAL CHANNELS
A1
B1
OE
BA
CE
BA
LE
BA
CP
BA
OE
AB
CE
AB
LE
AB
CP
AB
SW00132
FUNCTION TABLE
INPUTS
OUTPUTS
CE
XX
OE
XX
LE
XX
CP
XX
DATA
OUTPUTS
X H X X X Z Disabled
X
X
L
L
H
H
X
X
H
L
H
L
Transparent
H L L X X NC Hold
L
L
L
L
L
L
↑
↑
h
l
H
L
Clock + display
L
L
L
L
L
L
L
H
X
X
NC Hold
XX = AB for A-to-B direction, BA for B-to-A direction
H = HIGH voltage level
L = LOW voltage level
h = HIGH state must be present one setup time before the LOW-to-HIGH transition of CP
XX
l = LOW state must be present one setup time before the LOW-to-HIGH transition of CP
XX
X = Don’t care
↑ = LOW-to-HIGH level transition
NC = No change
Z = High impedance “off” state
Philips Semiconductors Product specification
74ALVCH1660118-bit universal bus transceiver (3-State)
1998 Sep 24
5
LOGIC SYMBOL (IEEE/IEC)
EN1
G2
2C3
C3
G2
EN4
3D
46D
56
55
1
2
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
SW00133
OE
AB
CP
AB
LE
AB
A0
A1
A2
A3
A4
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
G5
5C6
C6
G5
29
30
28
27
OE
BA
CP
BA
CE
BA
LE
BA
CE
AB
A5
24
26
33
31
A16
A17
B16
B17
1
BUSHOLD CIRCUIT
To internal circuit
V
CC
Data Input
SW00050
P1-P3P4-P6P7-P9P10-P12P13-P13

74ALVCH16601DGGS

Mfr. #:
Buy 74ALVCH16601DGGS
Manufacturer:
Nexperia
Description:
Bus Transceivers 18-Bit Universal Bus Transceiver, 3-State
Lifecycle:
New from this manufacturer.
Delivery:
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