MAX9692EUB+T

MAX9691/MAX9692/MAX9693
The timing diagram (Figure 3) illustrates the series of
events that complete the compare function, under
worst-case conditions. The top line of the diagram illus-
trates two latch-enable pulses. Each pulse is high for
the compare function and low for the latch function. The
first pulse demonstrates the compare function; part of
the input action takes place during the compare mode.
The second pulse demonstrates a compare function
interval during which there is no change in the input.
The leading edge of the input signal (illustrated as a
large-amplitude, small-overdrive pulse) switches the
comparator after time interval t
pd
. Output Q and Q tran-
sistors are similar in timing. The input signal must occur
at time t
s
before the latch falling edge, and must be
maintained for time t
h
after the edge to be acquired.
After t
h
, the output is no longer affected by the input sta-
tus until the latch is again strobed. A minimum latch
pulse width of t
pw(LE)
is needed for the strobe opera-
tion, and the output transitions occur after a time t
LE(±)
.
The MAX9691/MAX9692/MAX9693 will not false trip
(i.e., output invert) if one of the inputs is in the valid
common-mode range while the other input is outside
the common-mode range.
LATCH
ENABLE
DIFFERENTIAL
INPUT
VOLTAGE
Q
Q
LATCH
COMPARE
t
s
t
h
V
OD
V
IN
t
LE(+)
V
OS
50%
50%
50%
t
pw(LE)
t
pd
Figure 3. Timing Diagram
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
_______________________________________________________________________________________ 7
MAX9691/MAX9692/MAX9693
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
8 _______________________________________________________________________________________
Definition of Terms
V
OS
Input Offset Voltage. The voltage required
between the input terminals to obtain 0V dif-
ferential at the output.
V
IN
Input Voltage Pulse Amplitude
V
OD
Input Voltage Overdrive
t
pd+
Input to Output High Delay. The propagation
delay measured from the time the input signal
crosses the input offset voltage to the 50%
point of an output low-to-high transition.
t
pd-
Input to Output Low Delay. The propagation
delay measured from the time the input signal
crosses the input offset voltage to the 50%
point of an output high-to-low transition.
t
LE(+)
Latch-Enable to Output High Delay. The prop-
agation delay measured from the 50% point of
the latch-enable signal low-to-high transition
to the 50% point of an output low-to-high tran-
sition.
t
LE(-)
Latch-Enable to Output Low Delay. The prop-
agation delay measured from the 50% point of
the latch-enable signal low-to-high transition
to the 50% point of an output high-to-low tran-
sition.
t
pw
(LE)
Latch-Enable Pulse Width. The minimum time
the latch-enable signal must be high to acquire
and hold an input signal.
t
s
Setup Time. The minimum time before the
negative transition of the latch-enable pulse
that an input signal must be present to be ac-
quired and held at the outputs.
t
h
Hold Time. The minimum time after the nega-
tive transition of the latch-enable signal that
an input signal must remain unchanged to be
acquired and held at the output.
pd
Propagation Delay Skew. The difference in
propagation delay between the Q and Q out-
puts crossing each other in both directions.
P
DSP
Propagation Delay Dispersion. The change in
propagation delay as a result of the overdrive
of the input signal varying.
t
pdm
Propagation Delay Match (MAX9693 only).
The difference in propagation delay between
two separate channels.
PART
TEMP
RANGE
PIN-PACKAGE
MAX9692EUB -40°C to +85°C 10 µMAX
MAX9692ESE -40°C to +85°C 16 Narrow SO
MAX9692EPE -40°C to +85°C 16 PDIP
MAX9693ESE -40°C to +85°C 16 Narrow SO
MAX9693EEE -40°C to +85°C 16 QSOP
MAX9693EPE -40°C to +85°C 16 PDIP
Ordering Information (continued)Chip Information
PROCESS: BiCMOS
Note: Devices are also available in lead(Pb)-free/RoHS-compli-
ant packages. Specify lead-free by adding a “+” after the part
number.
MAX9691/MAX9692/MAX9693
Pin Configurations
DIP/SO/µMAX
MAX9691
Q OUT
Q OUTV
EE
1
2
8
7
GND1
GND2IN+
IN-
V
CC
3
4
6
5
TOP VIEW
µMAX
MAX9692
1
2
3
4
5
10
9
8
7
6
GND1
GND2
Q OUT
Q OUTN.C.
IN-
IN+
V
CC
V
EE
LE
PDIP/SO
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
GND1 GND2
N.C.
N.C.
N.C.
Q OUT
N.C.
N.C.
V
CC
IN+
LE
IN-
N.C.
N.C.
V
EE
MAX9692
MAX9693
DIP/SO/QSOP
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Q OUTA Q OUTB
Q OUTB
GND
LEB
LEB
V
CC
INB-
INB+
Q OUTA
GND
V
EE
LEA
LEA
INA-
INA+
Q OUT
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
_______________________________________________________________________________________ 9
Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a "+", "#", or
"-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE OUTLINE NO.
LAND
PATTERN NO.
8 µMAX U8+1 21-0036 90-0092
8 SO S8+2 21-0041 90-0096
8 PDIP P8+5 21-0043
10 µMAX U10+2 21-0061 90-0330
16 QSOP E16+1 21-0055 90-0167
16 SO S16+3 21-0041 90-0097
16 PDIP P16+1 21-0043

MAX9692EUB+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog Comparators Single Comparator
Lifecycle:
New from this manufacturer.
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