DS3901
Triple, 8-Bit NV Variable Resistor
with Dual Settings and User EEPROM
18 ____________________________________________________________________
Byte Write: A byte write consists of 8 bits of informa-
tion transferred from the master to the slave (MSB first)
plus a 1-bit acknowledgement from the slave to the
master. The 8 bits transmitted by the master are done
according to the bit write definition and the acknowl-
edgement is read using the bit read definition.
Byte Read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information that
are transferred (MSB first) from the slave to the master are
read by the master using the bit read definition above, and
the master transmits an ACK using the bit write definition
to receive additional data bytes. The master must NACK
the last byte read to terminate communication so the slave
will return control of SDA to the master.
Slave Address Byte: Each slave on the I
2
C bus
responds to a slave addressing byte sent immediately
following a START condition. The slave address byte
contains the slave address in the most significant 7 bits
and the R/W bit in the least significant bit.
The ADD_SEL pin and Slave Address register (9Fh)
determine the I
2
C slave address for the DS3901. If
ADD_SEL is low, then the slave address is fixed at A2h.
If ADD_SEL is high, then the slave address in the Slave
Address Register (9Fh) is used.
The LSB of the Slave Address Byte is the R/W bit. If the
R/W bit is 0, then the master indicates it will write data
to the slave. If R/W = 1, then the master will read data
from the slave. If an incorrect slave address is written,
the DS3901 will assume the master is communicating
with another I
2
C device and ignore the communication
until the next START condition is sent.
Memory Address: During an I
2
C write operation, the
master must transmit a memory address to identify the
memory location where the slave is to store the data.
The memory address is always the second byte trans-
mitted during a write operation following the slave
address byte.
I
2
C Communication
Writing a Single Byte to a Slave: The master must
generate a START condition, write the slave address
byte (R/W = 0), write the memory address, write the
byte of data, and generate a STOP condition.
Remember the master must read the slave’s acknowl-
edgement during all byte write operations.
Writing Multiple Bytes to a Slave: To write multiple
bytes to a slave the master generates a START condi-
tion, writes the slave address byte (R/W = 0), writes the
memory address, writes up to 8 data bytes, and gener-
ates a STOP condition.
The DS3901 is capable of writing up to 8 bytes (1 page
or row) with a single write transaction. This is internally
controlled by an address counter that allows data to be
written to consecutive addresses without transmitting a
memory address before each data byte is sent. The
address counter limits the write to one 8-byte page.
Attempts to write to additional pages of memory without
sending a STOP condition between pages result in the
address counter wrapping around to the beginning of
the present row. To prevent address wrapping from
occurring, the master must send a STOP condition at
the end of the page, and then wait for the bus free or
EEPROM write time to elapse. Then the master may
generate a new START condition and write the slave
address byte (R/W = 0) and the first memory address of
the next memory row before continuing to write data.
Acknowledge Polling: Any time an EEPROM page is
written, the DS3901 requires the EEPROM write time
(t
W
) after the STOP condition to write the contents of
the page to EEPROM. During the EEPROM write time,
the device will not acknowledge its slave address
because it is busy. It is possible to take advantage of
that phenomenon by repeatedly addressing the
DS3901, which allows the next page to be written as
soon as the DS3901 is ready to receive the data. The
alternative to acknowledge polling is to wait for a maxi-
mum period of t
W
to elapse before attempting to write
again to the device.
EEPROM Write Cycles: When EEPROM writes occur,
the DS3901 will write the whole EEPROM memory page
even if only a single byte on the page was modified.
Writes that do not modify all 8 bytes on the page are
allowed and do not corrupt the remaining bytes of
memory on the same page. Because the whole page is
written, bytes on the page that were not modified during
the transaction are still subject to a write cycle. This can
result in a whole page being worn out over time by
writing a single byte repeatedly. The DS3901’s EEPROM
write cycles are specified in the Nonvolatile Memory
Characteristics table. The specification shown is at the
worst-case temperature.
