DS3901
Triple, 8-Bit NV Variable Resistor
with Dual Settings and User EEPROM
4 _____________________________________________________________________
Note 1: All voltages referenced to ground.
Note 2: Guaranteed by design.
Note 3: I
STBY
specified for the inactive state measured with SDA = SCL = V
CC
, ADD_SEL = GND, BK_SEL, DIS, H0, H1, H2, L2, L0
floating.
Note 4: Absolute linearity is the deviation of a measured resistor-setting value from the expected value at each particular resistor
setting. Expected value is calculated by connecting a straight line from the measured minimum setting to the measured
maximum setting.
Note 5: Relative linearity is the deviation of the step size change between two LSB settings from the expected step size. The expected
LSB step size is the slope of the straight line from measured minimum position to measured maximum position.
Note 6: See the Typical Operating Characteristics.
Note 7: Timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I
2
C standard mode.
Note 8: CB—total capacitance of one bus line in picofarads.
Note 9: EEPROM write begins after a STOP condition occurs.
NONVOLATILE MEMORY CHARACTERISTICS
(V
CC
= +2.4V to +5.5V.)
