Nexperia
74AUP1G34
Low-power buffer
74AUP1G34 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved.
Product data sheet Rev. 7 — 28 March 2017
10 / 21
11.1 Waveforms and test circuit
Measurement points are given in Table 9 .
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Figure 10. The data input (A) to output (Y) propagation delays
Table 9. Measurement points
Supply voltage Output Input
V
CC
V
M
V
M
V
I
t
r
= t
f
0.8 V to 3.6 V 0.5 × V
CC
0.5 × V
CC
V
CC
≤ 3.0 ns
001aac521
DUT
R
T
V
I
V
O
V
EXT
V
CC
R
L
5 kΩ
C
L
G
Test data is given in Table 10 .
Definitions for test circuit:
R
L
= Load resistance.
C
L
= Load capacitance including jig and probe capacitance.
R
T
= Termination resistance should be equal to the output impedance Z
o
of the pulse generator.
V
EXT
= External voltage for measuring switching times.
Figure 11. Test circuit for measuring switching times
Table 10. Test data
Supply voltage Load V
EXT
V
CC
C
L
R
L
[1]
t
PLH
, t
PHL
t
PZH
, t
PHZ
t
PZL
, t
PLZ
0.8 V to 3.6 V 5 pF, 10 pF, 15 pF and 30 pF 5 kΩ or 1 MΩ open GND 2 × V
CC
[1] For measuring enable and disable times R
L
= 5 kΩ, for measuring propagation delays, setup and hold times and pulse width R
L
= 1 MΩ.
Nexperia
74AUP1G34
Low-power buffer
74AUP1G34 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved.
Product data sheet Rev. 7 — 28 March 2017
11 / 21
12 Package outline
UNIT
A
1
A
max.
A
2
A
3
b
p
LH
E
L
p
w yv
c eD
(1)
E
(1)
Z
(1)
θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
0.1
0
1.0
0.8
0.30
0.15
0.25
0.08
2.25
1.85
1.35
1.15
0.65
e
1
1.3
2.25
2.0
0.60
0.15
0.1 0.10.30.425
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
0.46
0.21
SOT353-1 MO-203 SC-88A
00-09-01
03-02-19
w M
b
p
D
Z
e
e
1
0.15
1 3
5 4
θ
A
A
2
A
1
L
p
(A
3
)
detail X
L
H
E
E
c
v M
A
X
A
y
1.5 3 mm0
scale
TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm
SOT353-1
1.1
Figure 12. Package outline SOT353-1 (TSSOP5)
Nexperia
74AUP1G34
Low-power buffer
74AUP1G34 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved.
Product data sheet Rev. 7 — 28 March 2017
12 / 21
References
Outline
version
European
projection
Issue date
IEC JEDEC JEITA
SOT886
MO-252
sot886_po
04-07-22
12-01-05
Unit
mm
max
nom
min
0.5 0.04 1.50
1.45
1.40
1.05
1.00
0.95
0.35
0.30
0.27
0.40
0.35
0.32
0.6
A
(1)
Dimensions (mm are the original dimensions)
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886
A
1
b
0.25
0.20
0.17
D E e e
1
0.5
L L
1
terminal 1
index area
D
E
e
1
e
A
1
b
L
L
1
e
1
0 1 2 mm
scale
1
6
2
5
3
4
6x
(2)
4x
(2)
A
Figure 13. Package outline SOT886 (XSON6)

74AUP1G34GX4Z

Mfr. #:
Manufacturer:
Nexperia
Description:
Low-Power Buffer 1-CH Non-Inverting CMOS 4-Pin X2SON T/R - Tape and Reel (Alt: 74AUP1G34GX4Z)
Lifecycle:
New from this manufacturer.
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