SiC783ACD
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Vishay Siliconix
S14-1639-Rev. B, 25-Aug-14
7
Document Number: 64902
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Shoot-Through Protection and Adaptive Dead Time
(AST)
The SiC783A has an internal adaptive logic to avoid shoot
through and optimize dead time. The shoot through
protection ensures that both high-side and low-side
MOSFETs are not turned on at the same time. The adaptive
dead time control operates as follows. The HS and LS gate
voltages are monitored to prevent the one turning on from
tuning on until the other's gate voltage is sufficiently low
(< 1 V). Built in delays also ensure that one power MOS is
completely off, before the other can be turned on. This
feature helps to adjust dead time as gate transitions change
with respect to output current and temperature.
Under Voltage Lockout (UVLO)
During the start up cycle, the UVLO disables the gate drive
holding high-side and low-side MOSFET gate low until the
input voltage rail has reached a point at which the logic
circuitry can be safely activated. The SiC783A also
incorporates logic to clamp the gate drive signals to zero
when the UVLO falling edge triggers the shutdown of the
device. As an added precaution, a 20 kΩ resistor is
connected between GH and PHASE to provide a discharge
path for the HS MOSFET.
FUNCTIONAL BLOCK DIAGRAM
Fig. 3 - SiC783A Functional Block Diagram
PWM
C
GND
20K
BOOT GH
V
SWH
GL
P
GND
+
-
V
ref
= 1 V
V
ref
= 1 V
GL
+
-
Anti-cross
conduction
control logic
V
DRV
PWM logic
control & state
machine
UVLO
Thermal monitor
& warning
THWn
ZCD_EN#
V
IN
PHASE
+
-
V
SWH
V
SWH
V
CIN
DSBL #
V
DRV
SiC783ACD
www.vishay.com
Vishay Siliconix
S14-1639-Rev. B, 25-Aug-14
8
Document Number: 64902
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
PWM TIMING DIAGRAM
Fig. 4 - Definition of PWM Logic and Tri-State
OPERATION TIMING DIAGRAM: DSBL#
Fig. 5 - DSBL# Propagation Delay
VTH_PWM_R
VTH_PWM_F
VTH_TRI_R
VTH_TRI_F
PWM
GH
GL
t
PD_OFF_GL
t
TSHO
t
PD_ON_GH
t
PD_OFF_GH
t
PD_ON_GL
t
TSHO
t
PD_TRI_R
t
PD_TRI_R
PWM
DSBL #
GH
GL
DSBL # Low to GH Falling Propagation Delay
t
DSBL # Low to GL Falling Propagation Delay
PWM
DSBL #
GH
GL
t
Disable
SiC783ACD
www.vishay.com
Vishay Siliconix
S14-1639-Rev. B, 25-Aug-14
9
Document Number: 64902
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
ELECTRICAL CHARACTERISTICS
(V
IN
= 12 V, F
SW
= 500 kHz, V
DRV
= V
CIN
= 5 V, L
O/P
= 0.33 µH / DCR 0.83 mΩ (IHLP-5050FD0R33-01), unless noted otherwise)
Fig. 6 - Efficiency vs. I
OUT
Fig. 7 - Power Stage Power Loss vs. I
OUT
78
80
82
84
86
88
90
92
94
0 2 4 6 8 10 12 14 16 18 20
EFFICENCY (%)
I
OUT
(A)
V
OUT
= 1.2 V; FCCM
V
OUT
= 1.2 V; ZCD
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
0 2 4 6 8 101214161820
Power Loss (W)
I
OUT
(A)

SIC783ACD-T1-GE3

Mfr. #:
Manufacturer:
Vishay / Siliconix
Description:
Gate Drivers 50A VRPwr Int Pw Stg DrMOS MLP66-40L
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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