Philips Semiconductors Product specification
74F534Octal D flip-flop, inverting (3-State)
2
2000 Aug 01 853-0374 24250
FEATURES
• 8-bit positive edge-triggered register
• 3-State inverting output buffers
• Common 3-State Output register
• Independent register and 3-State buffer operation
DESCRIPTION
The 74F534 is an 8-bit edge-triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by the Clock (CP) and Output Enable (OE) control
gates.
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q
output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active Low Output Enable (OE
) controls all eight 3-State buffers
independent of the latch operation. When OE
is Low, the latched or
transparent data appears at the outputs. When OE
is High, the
outputs are in high impedance “off” state, which means they will
neither drive nor load the bus.
TYPE
TYPICAL f
MAX
TYPICAL SUPPLY
CURRENT
(TOTAL)
74F534 165MHz 51mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL
RANGE
V
CC
= 5V ±10%,
T
amb
= 0°C to +70°C
PKG DWG #
20-Pin Plastic DIP N74F534N SOT146-1
20-Pin Plastic SOL N74F534D SOT163-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
D0 - D7 Data inputs 1.0/1.0 20µA/0.6mA
OE Output Enable input (active Low) 1.0/1.0 20µA/0.6mA
CP Clock Pulse input (active rising edge) 1.0/1.0 20µA/0.6mA
Q0 - Q7 Data outputs 150/40 3.0mA/24mA
NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High state and 0.6mA in the Low state.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
OE
Q0
D0
D1
Q
1
Q
2
D2
D3
Q
3Q4
GND
D4
D5
Q
5
Q
6
D6
D7
Q
7
V
CC
CP
SF00982
LOGIC SYMBOL
34781314
15129652
1
11 CP
OE
Q0
D0 D1
Q1
D2
Q2Q3
D3
Q4
D4
Q5
D5
17 18
1916
Q6
D6
Q7
D7
SF00984
V
CC
=Pin 20
GND=Pin 10
