BD3539FVM-TR

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2009.10 - Rev.
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Hi-performance Regulator IC Series for PCs
Termination Regulators
for DDR-SDRAMs
BD3539FVM,BD3539NUX
Description
BD3539FVM/NUX is a termination regulator compatible with JEDEC DDR1-SDRAM, DDR2-SDRAM, DDR3-SDRAM which
functions as a linear power supply incorporating an N-channel MOSFET and provides a sink/source current capability up to
1A respectively. A built-in high-speed OP-AMP specially designed offers an excellent transient response. Requires 3.3
volts (DDR2, DDR3) or 5.0 volts (DDR1, DDR2, DDR3) as a bias power supply to drive the N-channel MOSFET. Has an
independent reference voltage input pin (VDDQ) and an independent feedback pin (VTTS) to maintain the accuracy in
voltage required by JEDEC, and offers an excellent output voltage accuracy and load regulation. Also has a reference
power supply output pin (VREF) for DDR-SDRAM or a memory controller. When EN pin turns to “Low”, VTT output
becomes “Hi-Z” while VREF output is kept unchanged, compatible with “Self Refresh” state of DDR-SDRAM.
Features
1) Incorporates a push-pull power supply for termination (VTT)
2) Incorporates a reference voltage circuit (VREF)
3) Incorporates an enabler
4) Incorporates an under voltage lockout (UVLO)
5) Employs MSOP8 package : 2.9×4.0×0.9(mm) : BD3539FVM
6) Employs VSON008X2030 package : 2.0×3.0×0.6(mm) : BD3539NUX
7) Incorporates a thermal shutdown protector (TSD)
8) Operates with input voltage from 2.7 to 5.5 volts
9) Compatible with Dual Channel (DDR1, DDR2, DDR3)
10) Usable ceramic capacitor at output
Use
Power supply for DDR1- SDRAM (VCC=5V only)
Power supply for DDR2-SDRAM (VCC=3.3V or 5V)
Power supply for DDR3-SDRAM (VCC=3.3V or 5V)
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol
Limit
Unit
BD3539FVM BD3539NUX
Input Voltage VCC 7
*1*2
V
Enable Input Voltage VEN 7
*1*2
V
Termination Input Voltage VTT_IN 7
*1*2
V
VDDQ Reference Voltage VDDQ 7
*1*2
V
Output Current ITT 1 A
Power Dissipation1 Pd1 387.4
*3
242.0
*4
mW
Power Dissipation2 Pd2 587.4
*4
515.0
*5
mW
Power Dissipation3 Pd3 - 877.2
*6
mW
Operating Temperature Range Topr -30+100
Storage Temperature Range Tstg -55+150
Maximum Junction Temperature Tjmax +150
*1 Should not exceed Pd.
*2 Instantaneous surge voltage, back electromotive force and voltage under less than 10% duty cycle.
*3 With Ta25 (With no heat sink) θja=322.6/W
*4 With Ta25 when mounting a 70mm×70mm×1.6mm glass-epoxy substrate, with no heat sinkθja=212.8/W
*5 With Ta25 (With no heat sink) θja=516.5/W
*6 With Ta25 when mounting a 70mm×70mm×1.6mm glass-epoxy substrate 1-layer board, θja=242.7/W
*7 With Ta25 when mounting a 70mm×70mm×1.6mm glass-epoxy substrate 4-layer board
(copper foil density: 5505mm
2
(copper foil area in each layer) ), θja=142.5/W
No.09030EAT24
BD3539FVM,BD3539NUX
Technical Note
2/11
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2009.10 - Rev.
A
© 2009 ROHM Co., Ltd. All rights reserved.
Operating ConditionsTa=25℃)
Parameter Symbol
Limit
Unit
MIN MAX
Input Voltage VCC
2.7 5.5 V
Termination Input Voltage VTT_IN
1.0 5.5 V
VDDQ Reference Voltage VDDQ
1.0 2.75 V
Enable Input Voltage VEN
-0.3 5.5 V
Electrical Characteristics (Unless otherwise noted, Ta=25, VCC=3.3V, VEN=3V, VDDQ=1.5V, VTT_IN=1.5V
Parameter Symbol
Limit
Unit Condition
MIN TYP MAX
Standby Current IST - 0.5 1.0 mA VEN=0V
Bias Current ICC - 2 4 mA VEN=3V
[Enable]
High Level Enable Input Voltage VENHIGH 2.3 - 5.5 V
Low Level Enable Input Voltage VENLOW -0.3 - 0.8 V
Enable Pin Input Current IEN - 7 10 µA VEN=3V
[Termination]
Termination Output Voltage
(DDR3)
VTT3
1/2×VDDQ
-15m
1/2×VDDQ
1/2×VDDQ
+15m
V
ITT=-1.0A to 1.0A
Ta=0 to 100
Termination Output Voltage
(DDR2)
VTT2
1/2×VDDQ
-30m
1/2×VDDQ
1/2×VDDQ
+30m
V
VCC = 3.3V, VDDQ = 1.8V
VTT_IN = 1.8V
ITT=-1.0A to 1.0A
Ta=0 to 100
Termination Output Voltage
(DDR1)
VTT1
1/2×VDDQ
-30m
1/2×VDDQ
1/2×VDDQ
+30m
V
VCC = 5.0V, VDDQ = 2.5V
VTT_IN = 2.5V
ITT=-1.0A to 1.0A
Ta=0 to 100
Source current ITT+ 1.0 - - A
Sink current ITT- - - -1.0 A
Load Regulation VTT - - 30 mV ITT=-1.0A to 1.0A
Upper Side ON Resistance HRON - 0.35 0.65 Ω
Lower Side ON Resistance LRON - 0.35 0.65 Ω
[VDDQ]
Input Impedance ZVDDQ 140 200 260 kΩ
[VREF]
Output Voltage VREF
1/2×VDDQ
-15m
1/2×VDDQ
1/2×VDDQ
+15m
V
IREF=-25mA to 25mA
Ta=0 to 100
[UVLO]
Threshold Voltage VUVLO 2.30 2.45 2.60 V VCC : sweep up
Hysteresis Voltage VUVLO 100 160 220 mV VCC : sweep down
BD3539FVM,BD3539NUX
Technical Note
3/11
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2009.10 - Rev.
A
© 2009 ROHM Co., Ltd. All rights reserved.
Reference Data
600
650
700
750
800
850
900
-2 -1.5 -1 -0.5 0 0.5 1 1.5 2
ITT[A]
VTT [mV]
748.5
749.0
749.5
750.0
750.5
751.0
751.5
-20 -10 0 10 20
IREF[mA]
VREF [mV]
Fig.1 DDR3 (-1A1A)
10µsec/Div
VREF(50mV/div)
VTT(50mV/div)
ITT(1A/div)
sink
source
Fig.2 DDR3 (1A-1A)
10µsec/Div
VREF(50mV/div)
VTT(50mV/div)
ITT(1A/div)
sink
source
Fig.3 Input Sequence1
VCC
EN
VDDQ
VTT_IN
VTT
Fig.4 Input Sequence 2
VCC
EN
VDDQ
VTT_IN
VTT
Fig.5 Input Sequence 3
VCC
EN
VDDQ
VTT_IN
VTT
Fig.6 ITT-VTT (DDR3)
Fig.7 IREF-VREF (DDR3)
Fig.8 EN Soft Start
EN
VTT
200µsec/Div
Fig.9 VDDQ Soft Start
VTT
VDDQ
VREF
2sec/Div
2sec/Div
2sec/Div

BD3539FVM-TR

Mfr. #:
Manufacturer:
Description:
Power Management Specialized - PMIC MEMORY IC REG
Lifecycle:
New from this manufacturer.
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