TLE 4290
Data Sheet 9 Rev. 1.7, 2007-03-20
The power good circuit supervises the output voltage. In case V
Q
falls below the Power
Good switching threshold the Power Good output PG is set LOW after the power good
reaction time. The power good LOW signal is generated down to an output voltage
V
Q
to 1 V. A LOW signal at the power good pin informs that the battery was lost and memory
is no longer valid.
The feature should only be used in combination to a microcontroller with internal reset.
For the power good delay time after the output voltage of the regulator is above the reset
threshold, the reset signal is set High again. The reset delay time is defined by the reset
delay capacitor
C
D
at pin D.
The Power Good delay time is defined by the charging time of an external delay
capacitor
C
D
.
C
D
= (t
rd
× I
D,c
) / ΔV (1)
With:
•
C
D
= Power Good delay capacitor
•
t
rd
= Power Good delay time
• Δ
V = V
DU
, typical 1.8 V
•
I
D,c
= Charge current typical 6 μA
Figure 5 Power Good Timing
AED03074
Thermal
t
rd
Power-on Voltage Dip Secondary Overload
at OutputSpike
V
DL
V
Ι
V
D
V
PG
D, c
Ι
=
Vd
dt
V
Q
t
rr
<
rr
t
V
DU
at Input
Undervoltage
Shutdown
C
D
Power Good
Signal
Q,pgt_d
V
Q,pgt_i
V
