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843003AGI-01LFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
REVISION A 12/8/14
843003I-01 DATA SHEET
10 FemtoClock
®
Crystal-to-3.3V LVPECL Frequency Synthesizer
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are recom-
mended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that generate
ECL/LVPECL compatible outputs. Therefore, terminating resistors
(DC current path to ground) or current sources must be used for
functionality. These outputs are designed to drive 50Ω transmission
FIGURE 4B. LVPECL OUTPUT TERMINATIONFIGURE 4A. LVPECL OUTPUT TERMINATION
lines. Matched impedance techniques should be used to maximize
operating frequency and minimize signal distortion. Figures 4A
and 4B show two different layouts which are recommended only
as guidelines. Other suitable clock layouts may exist and it would
be recommended that the board designers simulate to guarantee
compatibility across all printed circuit and clock component process
variations.
INPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left fl oating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
REF_CLK INPUT:
For applications not requiring the use of the reference clock, it can
be left fl oating. Though not required, but for additional protection, a
1kΩ resistor can be tied from the REF_CLK to ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
OUTPUTS:
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
LVPECL OUTPUT
All unused LVPECL outputs can be left fl oating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left fl oating or terminated.
FemtoClock
®
Crystal-to-3.3V LVPECL Frequency Synthesizer
843003I-01 DATA SHEET
11 REVISION A 12/8/14
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843003I-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843003I-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 150mA = 519.75mW
• Power (outputs)
MAX
= 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 3 * 30.2mW = 90.6mW
Total Power
_MAX
(3.465V, with all outputs switching) = 519.75mW + 90.6mW = 610.35mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θ
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
JA
must be used. Assuming a
moderate air fl ow of 1 meter per second and a multi-layer board, the appropriate value is 65°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.610W * 65°C/W = 124.6°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the
type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θ
JA
FOR 24-PIN TSSOP, FORCED CONVECTION
θ
JA
by Velocity (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 70°C/W 65°C/W 62°C/W
REVISION A 12/8/14
843003I-01 DATA SHEET
12 FemtoClock
®
Crystal-to-3.3V LVPECL Frequency Synthesizer
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V
CCO
- 2V.
• For logic high, V
OUT
= V
OH_MAX
= V
CCO_MAX
– 1.0V
(V
CCO_MAX
- V
OH_MAX
)
= 1.0V
• For logic low, V
OUT
= V
OL_MAX
= V
CCO_MAX
– 1.7V
(V
CCO_MAX
- V
OL_MAX
)
= 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) = [(2V - (V
CCO_MAX
- V
OH_MAX
))
/R
L
] * (V
CCO_MAX
- V
OH_MAX
) =
[(2V - 1V)/50Ω] * 1V = 20.0mW
Pd_L = [(V
OL_MAX
– (V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) = [(2V - (V
CCO_MAX
- V
OL_MAX
))
/R
L
] * (V
CCO_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

843003AGI-01LFT

Mfr. #:
Buy 843003AGI-01LFT
Manufacturer:
Description:
Clock Synthesizer / Jitter Cleaner 3 LVPECL OUT SYNTHESIZER
Lifecycle:
New from this manufacturer.
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