Internally Trimmed
Integrated Circuit Multiplier
Data Sheet
AD532
Rev. E Document Feedback
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FEATURES
Pretrimmed to ±1.0% (AD532K)
No external components required
Guaranteed ±1.0% maximum 4-quadrant error (AD532K)
Differential inputs for (X
1
− X
2
) (Y
1
− Y
2
)/10 V transfer function
Monolithic construction, low cost
APPLICATIONS
Multiplication, division, squaring, square rooting
Algebraic computation
Power measurements
Instrumentation applications
Available in chip form
GENERAL DESCRIPTION
The AD532 is the first pretrimmed, single chip, monolithic
multiplier/divider. It guarantees a maximum multiplying error
of ±1.0% and a ±10 V output voltage without the need for any
external trimming resistors or output op amp. Because the AD532
is internally trimmed, its simplicity of use provides design
engineers with an attractive alternative to modular multipliers,
and its monolithic construction provides significant advantages
in size, reliability, and economy. Further, the AD532 can be a
direct replacement for other IC multipliers that require external
trim networks.
FLEXIBILITY OF OPERATION
The AD532 multiplies in four quadrants with a transfer function of
(X
1
− X
2
)(Y
1
− Y
2
)/10 V, divides in two quadrants with a 10 V Z/
(X
1
− X
2
) transfer function, and square roots in one quadrant
with a transfer function of
ZV10
. In addition to these basic
functions, the differential X and Y inputs provide significant
operating flexibility both for algebraic computation and transducer
instrumentation applications. Transfer functions, such as XY/10 V,
(X
2
− Y
2
)/10 V, ±X
2
/10 V, and 10 V Z/(X
1
− X
2
), are easily attained
and are extremely useful in many modulation and function
generation applications, as well as in trigonometric calculations
for airborne navigation and guidance applications, where the
monolithic construction and small size of the AD532 offer
considerable system advantages. In addition, the high common-
mode rejection ratio (CMRR) (75 dB) of the differential inputs
makes the AD532 especially well qualified for instrumentation
applications, as it can provide an output signal that is the product of
two transducer generated input signals.
FUNCTIONAL BLOCK DIAGRAM
(WITH Z TIED TO OUTPUT)
V
X
V
Y
X
1
X
2
Y
1
Y
2
RR
Z
OUTPUT
V
OS
10R
R
V
OUT
=
(X
1
– X
2
) (Y
1
– Y
2
)
10V
00502-003
X
Figure 1.
GUARANTEED PERFORMANCE OVER
TEMPERATURE
The AD532J and AD532K are specified for maximum multiplying
errors of ±2% and ±1% of full scale, respectively at 25°C, and
are rated for operation from 0°C to 70°C. The AD532S has a
maximum multiplying error of ±1% of full scale at 25°C; it is
also 100% tested to guarantee a maximum error of ±4% at the
extended operating temperature limits of −55°C and +125°C.
All devices are available in either a hermetically sealed TO-100
metal can or 14-lead D-14 side brazed ceramic DIP. The J, K,
and S grade chips are also available.
ADVANTAGES OF ON THE CHIP TRIMMING OF
THE MONOLITHIC AD532
1. True ratiometric trim for improved power supply rejection.
2. Reduced power requirements since no networks across
supplies are required.
3. More reliable because standard monolithic assembly
techniques can be used rather than more complex hybrid
approaches.
4. High impedance X and Y inputs with negligible circuit
loading.
5. Differential X and Y inputs for noise rejection and additional
computational flexibility.
